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feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32c5

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This commit is contained in:
yanzihan@espressif.com
2026-02-01 13:24:49 +08:00
committed by Jack
parent 025ec41dac
commit d0b1371e34
15 changed files with 336 additions and 25 deletions
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components/esp_hal_clock/esp32c5/include/hal/clk_gate_ll.h
+7 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -154,9 +154,10 @@ FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable)
typedef struct {
bool disable_uart0_clk; ///< Disable UART0 clock (when UART0 is not console)
bool disable_uart1_clk; ///< Disable UART1 clock (when UART1 is not console)
bool disable_mspi_flash_clk; ///< Disable MSPI flash clock (for PURE_RAM_APP)
bool disable_mspi_flash_clk; ///< Disable MSPI flash clock (for PURE_RAM_APP)
bool disable_crypto_periph_clk; ///< Disable crypto peripherals clock when TEE is not enabled
bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock and pad (when not enabled)
bool disable_pvt_clk; ///< Disable PVT clock
} periph_ll_clk_gate_config_t;
/**
@@ -201,6 +202,10 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
PCR.uhci_conf.uhci_clk_en = 0;
PCR.tcm_mem_monitor_conf.tcm_mem_monitor_clk_en = 0;
PCR.psram_mem_monitor_conf.psram_mem_monitor_clk_en = 0;
if (config->disable_pvt_clk) {
PCR.pvt_monitor_conf.pvt_monitor_clk_en = 0;
PCR.pvt_monitor_func_clk_conf.pvt_monitor_func_clk_en = 0;
}
PCR.ctrl_clk_out_en.val = 0;
if (config->disable_usb_serial_jtag) {