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fix(esp_system): enable linking with LLD on RISC-V targets

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Stefan Stipanovic
2026-08-13 21:23:36 +02:00
parent b2672c7937
commit d0ae774d59
17 changed files with 147 additions and 11 deletions
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components/riscv/vectors_clic.S
+6 -1
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@@ -29,11 +29,16 @@
.global _interrupt_handler
.global _panic_handler
.section .exception_vectors_table.text
.section .exception_vectors_table.text, "ax"
/* Prevent the compiler from generating 2-byte instruction in the vector tables */
.option push
.option norvc
/* The vector tables have a fixed layout, so keep linker relaxation from
* touching them: with relaxation enabled the assembler emits the .balign
* padding as R_RISCV_ALIGN-managed bytes, of which GNU ld may retain more
* than the exact amount, changing the table size between builds. */
.option norelax
/**
* Non-hardware vectored interrupt entry. MTVEC CSR points here.