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feat(i2s): support i2s on esp32p4

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This commit is contained in:
laokaiyao
2023-09-28 15:03:27 +08:00
parent 492c819357
commit cf889f3c6d
21 changed files with 1568 additions and 372 deletions
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components/soc/esp32c6/include/soc/i2s_struct.h
+1 -123
View File
@@ -240,34 +240,6 @@ typedef union {
uint32_t val;
} i2s_rx_conf1_reg_t;
/** Type of rx_clkm_conf register
* I2S RX clock configure register
*/
typedef union {
struct {
/** rx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S clock divider value
*/
uint32_t rx_clkm_div_num:8;
uint32_t reserved_8:18;
/** rx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Rx module clock enable signal.
*/
uint32_t rx_clk_active:1;
/** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/
uint32_t rx_clk_sel:2;
/** mclk_sel : R/W; bitpos: [29]; default: 0;
* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
* I2S_MCLK_OUT.
*/
uint32_t mclk_sel:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_rx_clkm_conf_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
@@ -609,37 +581,6 @@ typedef union {
uint32_t val;
} i2s_tx_conf1_reg_t;
/** Type of tx_clkm_conf register
* I2S TX clock configure register
*/
typedef union {
struct {
/** tx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
* (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
* a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
* (n+1)-div] + y * (n+1)-div.
*/
uint32_t tx_clkm_div_num:8;
uint32_t reserved_8:18;
/** tx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Tx module clock enable signal.
*/
uint32_t tx_clk_active:1;
/** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in.
*/
uint32_t tx_clk_sel:2;
/** clk_en : R/W; bitpos: [29]; default: 0;
* Set this bit to enable clk gate
*/
uint32_t clk_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_tx_clkm_conf_reg_t;
/** Type of tx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@@ -742,36 +683,6 @@ typedef union {
/** Group: RX clock and timing registers */
/** Type of rx_clkm_div_conf register
* I2S RX module clock divider configure register
*/
typedef union {
struct {
/** rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_RX_CLKM_DIV_Z is (a-b).
*/
uint32_t rx_clkm_div_z:9;
/** rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_RX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t rx_clkm_div_y:9;
/** rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t rx_clkm_div_x:9;
/** rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_RX_CLKM_DIV_YN1 is 1.
*/
uint32_t rx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_rx_clkm_div_conf_reg_t;
/** Type of rx_timing register
* I2S RX timing control register
*/
@@ -813,36 +724,6 @@ typedef union {
/** Group: TX clock and timing registers */
/** Type of tx_clkm_div_conf register
* I2S TX module clock divider configure register
*/
typedef union {
struct {
/** tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_TX_CLKM_DIV_Z is (a-b).
*/
uint32_t tx_clkm_div_z:9;
/** tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_TX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t tx_clkm_div_y:9;
/** tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t tx_clkm_div_x:9;
/** tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_TX_CLKM_DIV_YN1 is 1.
*/
uint32_t tx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_tx_clkm_div_conf_reg_t;
/** Type of tx_timing register
* I2S TX timing control register
*/
@@ -993,10 +874,7 @@ typedef struct i2s_dev_t {
volatile i2s_tx_conf_reg_t tx_conf;
volatile i2s_rx_conf1_reg_t rx_conf1;
volatile i2s_tx_conf1_reg_t tx_conf1;
volatile i2s_rx_clkm_conf_reg_t rx_clkm_conf;
volatile i2s_tx_clkm_conf_reg_t tx_clkm_conf;
volatile i2s_rx_clkm_div_conf_reg_t rx_clkm_div_conf;
volatile i2s_tx_clkm_div_conf_reg_t tx_clkm_div_conf;
uint32_t reserved_030[4];
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
uint32_t reserved_048[2];
components/soc/esp32h2/include/soc/i2s_struct.h
+1 -123
View File
@@ -240,34 +240,6 @@ typedef union {
uint32_t val;
} i2s_rx_conf1_reg_t;
/** Type of rx_clkm_conf register
* I2S RX clock configure register
*/
typedef union {
struct {
/** rx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S clock divider value
*/
uint32_t rx_clkm_div_num:8;
uint32_t reserved_8:18;
/** rx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Rx module clock enable signal.
*/
uint32_t rx_clk_active:1;
/** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
*/
uint32_t rx_clk_sel:2;
/** mclk_sel : R/W; bitpos: [29]; default: 0;
* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
* I2S_MCLK_OUT.
*/
uint32_t mclk_sel:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_rx_clkm_conf_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
@@ -607,37 +579,6 @@ typedef union {
uint32_t val;
} i2s_tx_conf1_reg_t;
/** Type of tx_clkm_conf register
* I2S TX clock configure register
*/
typedef union {
struct {
/** tx_clkm_div_num : R/W; bitpos: [7:0]; default: 2;
* Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
* (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
* a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
* (n+1)-div] + y * (n+1)-div.
*/
uint32_t tx_clkm_div_num:8;
uint32_t reserved_8:18;
/** tx_clk_active : R/W; bitpos: [26]; default: 0;
* I2S Tx module clock enable signal.
*/
uint32_t tx_clk_active:1;
/** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
* I2S_MCLK_in.
*/
uint32_t tx_clk_sel:2;
/** clk_en : R/W; bitpos: [29]; default: 0;
* Set this bit to enable clk gate
*/
uint32_t clk_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} i2s_tx_clkm_conf_reg_t;
/** Type of tx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@@ -740,36 +681,6 @@ typedef union {
/** Group: RX clock and timing registers */
/** Type of rx_clkm_div_conf register
* I2S RX module clock divider configure register
*/
typedef union {
struct {
/** rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_RX_CLKM_DIV_Z is (a-b).
*/
uint32_t rx_clkm_div_z:9;
/** rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_RX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t rx_clkm_div_y:9;
/** rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t rx_clkm_div_x:9;
/** rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_RX_CLKM_DIV_YN1 is 1.
*/
uint32_t rx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_rx_clkm_div_conf_reg_t;
/** Type of rx_timing register
* I2S RX timing control register
*/
@@ -811,36 +722,6 @@ typedef union {
/** Group: TX clock and timing registers */
/** Type of tx_clkm_div_conf register
* I2S TX module clock divider configure register
*/
typedef union {
struct {
/** tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
* I2S_TX_CLKM_DIV_Z is (a-b).
*/
uint32_t tx_clkm_div_z:9;
/** tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
* I2S_TX_CLKM_DIV_Y is (a%(a-b)).
*/
uint32_t tx_clkm_div_y:9;
/** tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
* of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
*/
uint32_t tx_clkm_div_x:9;
/** tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
* For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
* I2S_TX_CLKM_DIV_YN1 is 1.
*/
uint32_t tx_clkm_div_yn1:1;
uint32_t reserved_28:4;
};
uint32_t val;
} i2s_tx_clkm_div_conf_reg_t;
/** Type of tx_timing register
* I2S TX timing control register
*/
@@ -991,10 +872,7 @@ typedef struct {
volatile i2s_tx_conf_reg_t tx_conf;
volatile i2s_rx_conf1_reg_t rx_conf1;
volatile i2s_tx_conf1_reg_t tx_conf1;
volatile i2s_rx_clkm_conf_reg_t rx_clkm_conf;
volatile i2s_tx_clkm_conf_reg_t tx_clkm_conf;
volatile i2s_rx_clkm_div_conf_reg_t rx_clkm_div_conf;
volatile i2s_tx_clkm_div_conf_reg_t tx_clkm_div_conf;
uint32_t reserved_030[4];
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
uint32_t reserved_048[2];
components/soc/esp32p4/i2s_periph.c
+69
View File
@@ -11,4 +11,73 @@
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
[0] = {
.mck_out_sig = I2S0_MCLK_PAD_OUT_IDX,
.m_tx_bck_sig = I2S0_O_BCK_PAD_OUT_IDX,
.m_rx_bck_sig = I2S0_I_BCK_PAD_OUT_IDX,
.m_tx_ws_sig = I2S0_O_WS_PAD_OUT_IDX,
.m_rx_ws_sig = I2S0_I_WS_PAD_OUT_IDX,
.s_tx_bck_sig = I2S0_O_BCK_PAD_IN_IDX,
.s_rx_bck_sig = I2S0_I_BCK_PAD_IN_IDX,
.s_tx_ws_sig = I2S0_O_WS_PAD_IN_IDX,
.s_rx_ws_sig = I2S0_I_WS_PAD_IN_IDX,
.data_out_sigs[0] = I2S0_O_SD_PAD_OUT_IDX,
.data_out_sigs[1] = I2S0_O_SD1_PAD_OUT_IDX,
.data_in_sigs[0] = I2S0_I_SD_PAD_IN_IDX,
.data_in_sigs[1] = I2S0_I_SD1_PAD_IN_IDX,
.data_in_sigs[2] = I2S0_I_SD2_PAD_IN_IDX,
.data_in_sigs[3] = I2S0_I_SD3_PAD_IN_IDX,
.irq = -1,
.module = PERIPH_I2S0_MODULE,
},
[1] = {
.mck_out_sig = I2S1_MCLK_PAD_OUT_IDX,
.m_tx_bck_sig = I2S1_O_BCK_PAD_OUT_IDX,
.m_rx_bck_sig = I2S1_I_BCK_PAD_OUT_IDX,
.m_tx_ws_sig = I2S1_O_WS_PAD_OUT_IDX,
.m_rx_ws_sig = I2S1_I_WS_PAD_OUT_IDX,
.s_tx_bck_sig = I2S1_O_BCK_PAD_IN_IDX,
.s_rx_bck_sig = I2S1_I_BCK_PAD_IN_IDX,
.s_tx_ws_sig = I2S1_O_WS_PAD_IN_IDX,
.s_rx_ws_sig = I2S1_I_WS_PAD_IN_IDX,
.data_out_sigs[0] = I2S1_O_SD_PAD_OUT_IDX,
.data_out_sigs[1] = -1,
.data_in_sigs[0] = I2S1_I_SD_PAD_IN_IDX,
.data_in_sigs[1] = -1,
.data_in_sigs[2] = -1,
.data_in_sigs[3] = -1,
.irq = -1,
.module = PERIPH_I2S1_MODULE,
},
[2] = {
.mck_out_sig = I2S2_MCLK_PAD_OUT_IDX,
.m_tx_bck_sig = I2S2_O_BCK_PAD_OUT_IDX,
.m_rx_bck_sig = I2S2_I_BCK_PAD_OUT_IDX,
.m_tx_ws_sig = I2S2_O_WS_PAD_OUT_IDX,
.m_rx_ws_sig = I2S2_I_WS_PAD_OUT_IDX,
.s_tx_bck_sig = I2S2_O_BCK_PAD_IN_IDX,
.s_rx_bck_sig = I2S2_I_BCK_PAD_IN_IDX,
.s_tx_ws_sig = I2S2_O_WS_PAD_IN_IDX,
.s_rx_ws_sig = I2S2_I_WS_PAD_IN_IDX,
.data_out_sigs[0] = I2S2_O_SD_PAD_OUT_IDX,
.data_out_sigs[1] = -1,
.data_in_sigs[0] = I2S2_I_SD_PAD_IN_IDX,
.data_in_sigs[1] = -1,
.data_in_sigs[2] = -1,
.data_in_sigs[3] = -1,
.irq = -1,
.module = PERIPH_I2S2_MODULE,
},
};
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+34 -2
View File
@@ -71,6 +71,10 @@ config SOC_I2C_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@@ -433,7 +437,7 @@ config SOC_I2C_SUPPORT_RTC
config SOC_I2S_NUM
int
default 1
default 3
config SOC_I2S_HW_VERSION_2
bool
@@ -443,7 +447,7 @@ config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
config SOC_I2S_SUPPORTS_APLL
bool
default y
@@ -451,10 +455,38 @@ config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
bool
default y
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_PDM_MAX_TX_LINES
int
default 2
config SOC_I2S_PDM_MAX_RX_LINES
int
default 4
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
components/soc/esp32p4/include/soc/clk_tree_defs.h
+15
View File
@@ -150,6 +150,7 @@ typedef enum {
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
SOC_MOD_CLK_APLL, /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
@@ -334,6 +335,20 @@ typedef enum {
///////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APLL}
/**
* @brief I2S clock source enum
*/
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
components/soc/esp32p4/include/soc/i2s_struct.h
+95 -89
View File
@@ -277,6 +277,92 @@ typedef union {
uint32_t val;
} i2s_rx_pdm2pcm_conf_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
* I2S TX PDM bypass hp filter or not. The option has been removed.
*/
uint32_t tx_pdm_hp_bypass:1;
/** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
uint32_t tx_pdm_sinc_osr2:4;
/** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
* I2S TX PDM prescale for sigmadelta
*/
uint32_t tx_pdm_prescale:8;
/** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_hp_in_shift:2;
/** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_lp_in_shift:2;
/** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sinc_in_shift:2;
/** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sigmadelta_in_shift:2;
/** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
* I2S TX PDM sigmadelta dither2 value
*/
uint32_t tx_pdm_sigmadelta_dither2:1;
/** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
* I2S TX PDM sigmadelta dither value
*/
uint32_t tx_pdm_sigmadelta_dither:1;
/** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
* I2S TX PDM dac mode enable
*/
uint32_t tx_pdm_dac_2out_en:1;
/** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
* I2S TX PDM dac 2channel enable
*/
uint32_t tx_pdm_dac_mode_en:1;
/** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
* I2S TX PDM Converter enable
*/
uint32_t pcm2pdm_conv_en:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf_reg_t;
/** Type of tx_pcm2pdm_conf1 register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
uint32_t tx_pdm_fp:10;
/** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
* I2S TX PDM Fs
*/
uint32_t tx_pdm_fs:10;
/** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
* I2S_TX_IIR_HP_MULT12_5[2:0])
*/
uint32_t tx_iir_hp_mult12_5:3;
/** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
* I2S_TX_IIR_HP_MULT12_0[2:0])
*/
uint32_t tx_iir_hp_mult12_0:3;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf1_reg_t;
/** Type of rx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@@ -371,7 +457,7 @@ typedef union {
uint32_t val;
} i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register
/** Type of rx_eof_num register
* I2S RX data number control register.
*/
typedef union {
@@ -384,7 +470,7 @@ typedef union {
uint32_t reserved_12:20;
};
uint32_t val;
} i2s_rxeof_num_reg_t;
} i2s_rx_eof_num_reg_t;
/** Group: TX Control and configuration registers */
@@ -530,89 +616,6 @@ typedef union {
uint32_t val;
} i2s_tx_conf1_reg_t;
/** Type of tx_pcm2pdm_conf register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
* I2S TX PDM OSR2 value
*/
uint32_t tx_pdm_sinc_osr2:4;
/** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
* I2S TX PDM prescale for sigmadelta
*/
uint32_t tx_pdm_prescale:8;
/** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_hp_in_shift:2;
/** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_lp_in_shift:2;
/** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sinc_in_shift:2;
/** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
* I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
*/
uint32_t tx_pdm_sigmadelta_in_shift:2;
/** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
* I2S TX PDM sigmadelta dither2 value
*/
uint32_t tx_pdm_sigmadelta_dither2:1;
/** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
* I2S TX PDM sigmadelta dither value
*/
uint32_t tx_pdm_sigmadelta_dither:1;
/** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
* I2S TX PDM dac mode enable
*/
uint32_t tx_pdm_dac_2out_en:1;
/** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
* I2S TX PDM dac 2channel enable
*/
uint32_t tx_pdm_dac_mode_en:1;
/** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
* I2S TX PDM Converter enable
*/
uint32_t pcm2pdm_conv_en:1;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf_reg_t;
/** Type of tx_pcm2pdm_conf1 register
* I2S TX PCM2PDM configuration register
*/
typedef union {
struct {
/** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
* I2S TX PDM Fp
*/
uint32_t tx_pdm_fp:10;
/** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
* I2S TX PDM Fs
*/
uint32_t tx_pdm_fs:10;
/** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
* I2S_TX_IIR_HP_MULT12_5[2:0])
*/
uint32_t tx_iir_hp_mult12_5:3;
/** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
* The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
* I2S_TX_IIR_HP_MULT12_0[2:0])
*/
uint32_t tx_iir_hp_mult12_0:3;
uint32_t reserved_26:6;
};
uint32_t val;
} i2s_tx_pcm2pdm_conf1_reg_t;
/** Type of tx_tdm_ctrl register
* I2S TX TDM mode control register
*/
@@ -845,7 +848,7 @@ typedef union {
uint32_t val;
} i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
/** Type of conf_single_data register
* I2S signal data register
*/
typedef union {
@@ -856,7 +859,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */
@@ -986,8 +989,8 @@ typedef struct {
volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
volatile i2s_rx_eof_num_reg_t rx_eof_num;
volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf;
volatile i2s_fifo_cnt_reg_t fifo_cnt;
@@ -996,6 +999,9 @@ typedef struct {
volatile i2s_date_reg_t date;
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
extern i2s_dev_t I2S2;
#ifndef __cplusplus
_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
components/soc/esp32p4/include/soc/soc_caps.h
+12 -7
View File
@@ -50,6 +50,8 @@
#define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 //TODO: IDF-6508
#define SOC_RMT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476
// #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551
// #define SOC_GPSPI_SUPPORTED 1 //TODO: IDF-7502, TODO: IDF-7503
// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510
@@ -240,16 +242,19 @@
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
//TODO: IDF-6508
#define SOC_I2S_NUM (1U)
#define SOC_I2S_NUM (3U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_APLL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_RX (1)
#define SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER (1)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2) // On I2S0
#define SOC_I2S_PDM_MAX_RX_LINES (4) // On I2S0
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)