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Merge branch 'feature/h2_twai_support' into 'master'

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twai: h2 support twai driver

Closes IDF-6217 and IDF-6673

See merge request espressif/esp-idf!22174
This commit is contained in:
Wan Lei
2023-02-21 11:43:51 +08:00
parent 75a82988f1 fdeeced62c
commit cf5387fc76
17 changed files with 141 additions and 326 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+4
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@@ -27,6 +27,10 @@ config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
config SOC_GPTIMER_SUPPORTED
bool
default y
components/soc/esp32h2/include/soc/clk_tree_defs.h
+2 -2
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@@ -389,8 +389,8 @@ typedef enum {
* @brief TWAI clock source
*/
typedef enum {
TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
components/soc/esp32h2/include/soc/gpio_sig_map.h
+6 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -135,14 +135,14 @@
#define RMT_SIG_IN1_IDX 72
#define RMT_SIG_OUT1_IDX 72
#define MODEM_DIAG9_IDX 72
#define CAN0_RX_IDX 73
#define CAN0_TX_IDX 73
#define TWAI_RX_IDX 73
#define TWAI_TX_IDX 73
#define MODEM_DIAG10_IDX 73
#define CAN0_BUS_OFF_ON_IDX 74
#define TWAI_BUS_OFF_ON_IDX 74
#define MODEM_DIAG11_IDX 74
#define CAN0_CLKOUT_IDX 75
#define TWAI_CLKOUT_IDX 75
#define MODEM_DIAG12_IDX 75
#define CAN0_STANDBY_IDX 76
#define TWAI_STANDBY_IDX 76
#define MODEM_DIAG13_IDX 76
#define CTE_ANT6_IDX 77
#define CTE_ANT7_IDX 78
components/soc/esp32h2/include/soc/soc_caps.h
+1 -2
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@@ -32,7 +32,7 @@
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-6217
#define SOC_TWAI_SUPPORTED 1
// #define SOC_BT_SUPPORTED 1 // TODO: IDF-6416
// #define SOC_IEEE802154_SUPPORTED 1 // TODO: IDF-6577
#define SOC_GPTIMER_SUPPORTED 1
@@ -359,7 +359,6 @@
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
#define SOC_TIMER_SUPPORT_ETM (1)
// TODO: IDF-6217 (Copy from esp32c6, need check)
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_CONTROLLER_NUM 1
#define SOC_TWAI_CLK_SUPPORT_XTAL 1
components/soc/esp32h2/twai_periph.c
+22
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@@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/twai_periph.h"
#include "soc/gpio_sig_map.h"
const twai_controller_signal_conn_t twai_controller_periph_signals = {
.controllers = {
[0] = {
.module = PERIPH_TWAI0_MODULE,
.irq_id = ETS_TWAI0_INTR_SOURCE,
.tx_sig = TWAI_TX_IDX,
.rx_sig = TWAI_RX_IDX,
.bus_off_sig = TWAI_BUS_OFF_ON_IDX,
.clk_out_sig = TWAI_CLKOUT_IDX,
.stand_by_sig = TWAI_STANDBY_IDX,
}
}
};
components/soc/esp32h4/include/soc/clk_tree_defs.h
-15
View File
@@ -296,21 +296,6 @@ typedef enum {
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of TWAI
*/
#define SOC_TWAI_CLKS {SOC_MOD_CLK_APB}
/**
* @brief TWAI clock source
*/
typedef enum {
TWAI_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
components/soc/esp32h4/include/soc/twai_struct.h
-209
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@@ -1,209 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* ---------------------------- Register Layout ------------------------------ */
/* The TWAI peripheral's registers are 8bits, however the ESP32-H4 can only access
* peripheral registers every 32bits. Therefore each TWAI register is mapped to
* the least significant byte of every 32bits.
*/
typedef volatile struct twai_dev_s {
//Configuration and Control Registers
union {
struct {
uint32_t rm: 1; /* MOD.0 Reset Mode */
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
uint32_t at: 1; /* CMR.1 Abort Transmission */
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
uint32_t dos: 1; /* SR.1 Data Overrun Status */
uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */
uint32_t tcs: 1; /* SR.3 Transmission Complete Status */
uint32_t rs: 1; /* SR.4 Receive Status */
uint32_t ts: 1; /* SR.5 Transmit Status */
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
uint32_t reserved13: 1; /* Internal Reserved */
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
struct {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
#endif
extern twai_dev_t TWAI;
#ifdef __cplusplus
}
#endif