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refactor(uart): split UART HAL into separate component

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This commit is contained in:
Song Ruo Jing
2026-01-04 16:02:57 +08:00
parent 68bef4ffa2
commit ce475d901d
78 changed files with 902 additions and 819 deletions
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components/esp_hal_uart/esp32p4/include/hal/uart_ll.h
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components/esp_hal_uart/esp32p4/include/hal/uhci_ll.h
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for UHCI register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/misc.h"
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
UHCI_RX_LEN_EOF = 0x4,
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
/**
* @brief Enable the bus clock for UHCI module
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
HP_SYS_CLKRST.soc_clk_ctrl2.reg_uhci_apb_clk_en = enable;
HP_SYS_CLKRST.soc_clk_ctrl1.reg_uhci_sys_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_enable_bus_clock(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_uhci_ll_enable_bus_clock(__VA_ARGS__); \
} while(0)
/**
* @brief Reset the UHCI module
*
* @param group_id Group ID
*/
static inline void _uhci_ll_reset_register(int group_id)
{
(void)group_id;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uhci = 1;
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uhci = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define uhci_ll_reset_register(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_uhci_ll_reset_register(__VA_ARGS__); \
} while(0)
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
hw->conf0.clk_en = 1;
conf0_reg.val = 0;
conf0_reg.clk_en = 1;
hw->conf0.val = conf0_reg.val;
hw->conf1.val = 0;
}
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
hw->conf0.uart_sel = uart_num;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
{
if (seper_char->sub_chr_en) {
hw->conf0.seper_en = 1;
typeof(hw->esc_conf0) esc_conf0_reg;
esc_conf0_reg.val = hw->esc_conf0.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_char, seper_char->seper_chr);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char0, seper_char->sub_chr1);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char1, seper_char->sub_chr2);
hw->esc_conf0.val = esc_conf0_reg.val;
hw->escape_conf.tx_c0_esc_en = 1;
hw->escape_conf.rx_c0_esc_en = 1;
} else {
hw->conf0.seper_en = 0;
hw->escape_conf.val = 0;
}
}
static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = 1;
}
if (eof_mode & UHCI_RX_IDLE_EOF) {
hw->conf0.uart_idle_eof_en = 1;
}
if (eof_mode & UHCI_RX_LEN_EOF) {
hw->conf0.len_eof_en = 1;
}
}
static inline void uhci_ll_rx_set_packet_threshold(uhci_dev_t *hw, uint16_t length)
{
hw->pkt_thres.pkt_thrs = length;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_uart/esp32p4/uart_periph.c
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/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/uart_periph.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/uart_reg.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART0
.pins = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = UART0_TXD_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = UART0_RXD_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = UART0_RTS_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = UART0_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = UART0_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = UART0_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
// HP UART1
.pins = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = UART1_TXD_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = UART1_RXD_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = UART1_RTS_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = UART1_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = UART1_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = UART1_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
{
// HP UART2
.pins = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U2TXD_GPIO_NUM,
.iomux_func = U2TXD_MUX_FUNC,
.input = 0,
.signal = UART2_TXD_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U2RXD_GPIO_NUM,
.iomux_func = U2RXD_MUX_FUNC,
.input = 1,
.signal = UART2_RXD_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U2RTS_GPIO_NUM,
.iomux_func = U2RTS_MUX_FUNC,
.input = 0,
.signal = UART2_RTS_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U2CTS_GPIO_NUM,
.iomux_func = U2CTS_MUX_FUNC,
.input = 1,
.signal = UART2_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U2DTR_GPIO_NUM,
.iomux_func = U2DTR_MUX_FUNC,
.input = 0,
.signal = UART2_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U2DSR_GPIO_NUM,
.iomux_func = U2DSR_MUX_FUNC,
.input = 1,
.signal = UART2_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART2_INTR_SOURCE,
},
{
// HP UART3
.pins = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U3TXD_GPIO_NUM,
.iomux_func = U3TXD_MUX_FUNC,
.input = 0,
.signal = UART3_TXD_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U3RXD_GPIO_NUM,
.iomux_func = U3RXD_MUX_FUNC,
.input = 1,
.signal = UART3_RXD_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U3RTS_GPIO_NUM,
.iomux_func = U3RTS_MUX_FUNC,
.input = 0,
.signal = UART3_RTS_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U3CTS_GPIO_NUM,
.iomux_func = U3CTS_MUX_FUNC,
.input = 1,
.signal = UART3_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U3DTR_GPIO_NUM,
.iomux_func = U3DTR_MUX_FUNC,
.input = 0,
.signal = UART3_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U3DSR_GPIO_NUM,
.iomux_func = U3DSR_MUX_FUNC,
.input = 1,
.signal = UART3_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART3_INTR_SOURCE,
},
{
// HP UART4
.pins = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U4TXD_GPIO_NUM,
.iomux_func = U4TXD_MUX_FUNC,
.input = 0,
.signal = UART4_TXD_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U4RXD_GPIO_NUM,
.iomux_func = U4RXD_MUX_FUNC,
.input = 1,
.signal = UART4_RXD_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U4RTS_GPIO_NUM,
.iomux_func = U4RTS_MUX_FUNC,
.input = 0,
.signal = UART4_RTS_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U4CTS_GPIO_NUM,
.iomux_func = U4CTS_MUX_FUNC,
.input = 1,
.signal = UART4_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U4DTR_GPIO_NUM,
.iomux_func = U4DTR_MUX_FUNC,
.input = 0,
.signal = UART4_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U4DSR_GPIO_NUM,
.iomux_func = U4DSR_MUX_FUNC,
.input = 1,
.signal = UART4_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART4_INTR_SOURCE,
},
{
// LP UART0
.pins = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = LP_U0TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC,
.input = 0,
.signal = LP_UART_TXD_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = LP_U0RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC,
.input = 1,
.signal = LP_UART_RXD_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = LP_U0RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC,
.input = 0,
.signal = LP_UART_RTSN_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = LP_U0CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC,
.input = 1,
.signal = LP_UART_CTSN_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = LP_U0DTR_GPIO_NUM,
.iomux_func = LP_U0DTR_MUX_FUNC,
.input = 0,
.signal = LP_UART_DTRN_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = LP_U0DSR_GPIO_NUM,
.iomux_func = LP_U0DSR_MUX_FUNC,
.input = 1,
.signal = LP_UART_DSRN_PAD_IN_IDX,
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
},
};
/**
* UART registers to be saved during sleep retention
*
* Reset TXFIFO and RXFIFO
* UART registers require set the reg_update bit to make the configuration take effect
*
* UART_INT_ENA_REG, UART_CLKDIV_SYNC_REG, UART_RX_FILT_REG, UART_CONF0_SYNC_REG, UART_CONF1_REG,
* UART_HWFC_CONF_SYNC_REG, UART_SLEEP_CONF0_REG, UART_SLEEP_CONF1_REG, UART_SLEEP_CONF2_REG,
* UART_SWFC_CONF0_SYNC_REG, UART_SWFC_CONF1_REG, UART_TXBRK_CONF_SYNC_REG, UART_IDLE_CONF_SYNC_REG,
* UART_RS485_CONF_SYNC_REG, UART_AT_CMD_PRECNT_SYNC_REG, UART_AT_CMD_POSTCNT_SYNC_REG, UART_AT_CMD_GAPTOUT_SYNC_REG,
* UART_AT_CMD_CHAR_SYNC_REG, UART_MEM_CONF_REG, UART_TOUT_CONF_SYNC_REG, UART_CLK_CONF_REG, UART_ID_REG
*/
#define UART_RETENTION_ADDR_MAP_REGS_CNT 22
#define UART_RETENTION_REGS_BASE(i) UART_INT_ENA_REG(i)
static const uint32_t uart_regs_map[4] = {0x807fff6d, 0x10, 0x0, 0x0};
#define UART_SLEEP_RETENTION_ENTRIES(uart_num) { \
[0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_UART_LINK(0x00), \
UART_RETENTION_REGS_BASE(uart_num), UART_RETENTION_REGS_BASE(uart_num), \
UART_RETENTION_ADDR_MAP_REGS_CNT, 0, 0, \
uart_regs_map[0], uart_regs_map[1], \
uart_regs_map[2], uart_regs_map[3] \
), \
.owner = ENTRY(0) }, \
[1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_UART_LINK(0x01), \
UART_REG_UPDATE_REG(uart_num), UART_REG_UPDATE, \
UART_REG_UPDATE_M, 1, 0 \
), \
.owner = ENTRY(0) }, \
[2] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_UART_LINK(0x02), \
UART_REG_UPDATE_REG(uart_num), 0x0, \
UART_REG_UPDATE_M, 1, 0 \
), \
.owner = ENTRY(0) }, \
}
static const regdma_entries_config_t uart0_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(0);
static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(1);
static const regdma_entries_config_t uart2_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(2);
static const regdma_entries_config_t uart3_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(3);
static const regdma_entries_config_t uart4_regdma_entries[] = UART_SLEEP_RETENTION_ENTRIES(4);
const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_UART0,
.regdma_entry_array = uart0_regdma_entries,
.array_size = ARRAY_SIZE(uart0_regdma_entries),
},
[1] = {
.module = SLEEP_RETENTION_MODULE_UART1,
.regdma_entry_array = uart1_regdma_entries,
.array_size = ARRAY_SIZE(uart1_regdma_entries),
},
[2] = {
.module = SLEEP_RETENTION_MODULE_UART2,
.regdma_entry_array = uart2_regdma_entries,
.array_size = ARRAY_SIZE(uart2_regdma_entries),
},
[3] = {
.module = SLEEP_RETENTION_MODULE_UART3,
.regdma_entry_array = uart3_regdma_entries,
.array_size = ARRAY_SIZE(uart3_regdma_entries),
},
[4] = {
.module = SLEEP_RETENTION_MODULE_UART4,
.regdma_entry_array = uart4_regdma_entries,
.array_size = ARRAY_SIZE(uart4_regdma_entries),
},
};