diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h index 1352205bab1..9c0c219e399 100644 --- a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h @@ -12,9 +12,20 @@ #include "soc/soc.h" #include "soc/reset_reasons.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/hp_alive_sys_struct.h" +#include "soc/bus_monitor_struct.h" +#include "soc/cnnt_sys_struct.h" #include "soc/lp_clkrst_struct.h" #include "soc/lp_clkrst_reg.h" -#include "soc/hp_sys_clkrst_struct.h" +#include "soc/lp_peri_clkrst_struct.h" +#include "soc/lp_gpio_struct.h" +#include "soc/usb_serial_jtag_struct.h" +#include "soc/tee_struct.h" +#include "soc/lp_tee_struct.h" +#include "soc/hp_apm_struct.h" +#include "soc/hp_mem_apm_struct.h" +#include "soc/cpu_apm_struct.h" +#include "soc/lp_apm_struct.h" #ifdef __cplusplus extern "C" { @@ -58,6 +69,171 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_25m_clk_en(bool enable) { HP_SYS_CLKRST.ref_25m_ctrl0.reg_ref_25m_clk_en = enable; } + +typedef struct { + bool disable_uart0_clk; ///< Gate UART0 when it is not the console UART + bool disable_uart1_clk; ///< Gate UART1 when it is not the console UART + bool disable_uart2_clk; ///< Gate UART2 when it is not the console UART + bool disable_uart3_clk; ///< Gate UART3 when it is not the console UART + bool disable_mspi_flash_clk; ///< Gate MSPI flash clocks (e.g. PURE_RAM_APP) + bool keep_psram_hp_clk; ///< Keep PSRAM MSPI root clocks when CONFIG_SPIRAM + bool disable_assist_clk; ///< Gate bus monitor (assist) clocks when PC record unused + bool disable_crypto_periph_clk; ///< Gate crypto accelerators when TEE does not own them + bool disable_usb_serial_jtag; ///< Gate USB Serial/JTAG when disabled in menuconfig +} periph_ll_clk_gate_config_t; + +/** + * @brief Turn off unused peripheral root clocks after reset (HP_SYS_CLKRST + LP cleanup). + * + * Skips HP peripheral gating on CPU-local reset reasons so debug / SW reset keep clocks aligned + * with retained peripheral state. Does not touch CPU/cache/ICM/intrmtx/iomux skeleton clocks. + */ +static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config) +{ + const bool skip_hp_periph_gate = (rst_reason == RESET_REASON_CPU_MWDT) || + (rst_reason == RESET_REASON_CPU_SW) || + (rst_reason == RESET_REASON_CPU_RWDT) || + (rst_reason == RESET_REASON_CPU_JTAG) || + (rst_reason == RESET_REASON_CPU_LOCKUP); + + if (!skip_hp_periph_gate) { + // UART0~3 + if (config->disable_uart0_clk) { + HP_SYS_CLKRST.uart0_ctrl0.reg_uart0_sys_clk_en = 0; + HP_SYS_CLKRST.uart0_ctrl0.reg_uart0_apb_clk_en = 0; + HP_SYS_CLKRST.uart0_ctrl0.reg_uart0_clk_en = 0; + } + if (config->disable_uart1_clk) { + HP_SYS_CLKRST.uart1_ctrl0.reg_uart1_sys_clk_en = 0; + HP_SYS_CLKRST.uart1_ctrl0.reg_uart1_apb_clk_en = 0; + HP_SYS_CLKRST.uart1_ctrl0.reg_uart1_clk_en = 0; + } + if (config->disable_uart2_clk) { + HP_SYS_CLKRST.uart2_ctrl0.reg_uart2_sys_clk_en = 0; + HP_SYS_CLKRST.uart2_ctrl0.reg_uart2_apb_clk_en = 0; + HP_SYS_CLKRST.uart2_ctrl0.reg_uart2_clk_en = 0; + } + if (config->disable_uart3_clk) { + HP_SYS_CLKRST.uart3_ctrl0.reg_uart3_sys_clk_en = 0; + HP_SYS_CLKRST.uart3_ctrl0.reg_uart3_apb_clk_en = 0; + HP_SYS_CLKRST.uart3_ctrl0.reg_uart3_clk_en = 0; + } + HP_ALIVE_SYS.hp_pad_uart0_ctrl.hp_pad_uart0_slp_clk_en = 0; + HP_ALIVE_SYS.hp_pad_uart1_ctrl.hp_pad_uart1_slp_clk_en = 0; + HP_ALIVE_SYS.hp_pad_uart2_ctrl.hp_pad_uart2_slp_clk_en = 0; + HP_ALIVE_SYS.hp_pad_uart3_ctrl.hp_pad_uart3_slp_clk_en = 0; + // ETM + HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_en = 0; + // Trace & Bus Monitor (0) + HP_SYS_CLKRST.trace_ctrl0.reg_trace_cpu_clk_en = 0; + HP_SYS_CLKRST.trace_ctrl0.reg_trace_sys_clk_en = 0; + // Assist Debug + if (config->disable_assist_clk) { + BUS_MONITOR.clock_gate.clk_en = 0; + } + // AXI DMA / AHB DMA / REGDMA / GDMA + HP_SYS_CLKRST.axi_pdma_ctrl0.reg_axi_pdma_sys_clk_en = 0; + HP_SYS_CLKRST.ahb_pdma_ctrl0.reg_ahb_pdma_sys_clk_en = 0; + HP_SYS_CLKRST.regdma_ctrl0.reg_regdma_sys_clk_en = 0; + HP_ALIVE_SYS.hp_pad_parlio_ctrl.hp_pad_parlio_tx_clk_en = 0; + HP_ALIVE_SYS.hp_pad_parlio_ctrl.hp_pad_parlio_rx_clk_en = 0; + // I2S0-1 + HP_ALIVE_SYS.hp_pad_i2s0_ctrl.hp_pad_i2s0_mclk_en = 0; + HP_ALIVE_SYS.hp_pad_i2s1_ctrl.hp_pad_i2s1_mclk_en = 0; + // TIMG0-1 + HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_apb_clk_en = 0; + HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_t0_clk_en = 0; + HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_t1_clk_en = 0; + HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_wdt_clk_en = 0; + HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_apb_clk_en = 0; + HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_t0_clk_en = 0; + HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_t1_clk_en = 0; + HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_wdt_clk_en = 0; + // LCDCAM + /* + * Default lcdcam_lcdcam_ctrl0: + * reg_lcdcam_clk_src_sel: 1 (BBPLL 120 MHz path, shared by LCD and CAM) + * reg_lcdcam_clk_div_num: 1 (divide by 2 → 60 MHz) + */ + HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 1; + HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_div_num = 1; + // ASRC + HP_SYS_CLKRST.ahb_asrc_ctrl0.reg_ahb_asrc_sys_clk_en = 0; + // Flash + if (config->disable_mspi_flash_clk) { + HP_SYS_CLKRST.flash_ctrl0.reg_flash_sys_clk_en = 0; + HP_SYS_CLKRST.flash_ctrl0.reg_flash_pll_clk_en = 0; + HP_SYS_CLKRST.flash_ctrl0.reg_flash_core_clk_en = 0; + } + // PSRAM + if (!config->keep_psram_hp_clk) { + HP_SYS_CLKRST.psram_ctrl0.reg_psram_sys_clk_en = 0; + HP_SYS_CLKRST.psram_ctrl0.reg_psram_pll_clk_en = 0; + HP_SYS_CLKRST.psram_ctrl0.reg_psram_core_clk_en = 0; + } + // MSPI + if (config->disable_mspi_flash_clk && !config->keep_psram_hp_clk) { + HP_SYS_CLKRST.mspi_pad_ctrl0.reg_mspi_pad_ctrl_apb_clk_en = 0; + } + // GPSPI + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_sys_clk_en = 0; + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_apb_clk_en = 0; + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_hs_clk_en = 0; + HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_mst_clk_en = 0; + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_sys_clk_en = 0; + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_apb_clk_en = 0; + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_hs_clk_en = 0; + HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_mst_clk_en = 0; + // HP I2C master + HP_SYS_CLKRST.hp_i2cmst_ctrl0.reg_hp_i2cmst_apb_clk_en = 0; + // Crypto + security monitors (TEE/APM) + if (config->disable_crypto_periph_clk) { + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_aes_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sha_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_rsa_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_ds_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_ecc_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_hmac_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_ecdsa_clk_en = 0; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_rma_clk_en = 0; + HP_SYS_CLKRST.key_manager_ctrl0.reg_key_manager_sys_clk_en = 0; + HP_SYS_CLKRST.key_manager_ctrl0.reg_crypto_km_clk_en = 0; + TEE.clock_gate.clk_en = 0; + LP_TEE.clock_gate.clk_en = 0; + HP_APM.clock_gate.clk_en = 0; + HP_MEM_APM.clock_gate.clk_en = 0; + CPU_APM.clock_gate.clk_en = 0; + } + // UTMI + CNNT_SYS_REG.sys_usb_otg20_ctrl.sys_usb_otg20_utmifs_clk_en = 0; + // USB-Serial-JTAG + if (config->disable_usb_serial_jtag) { + USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; + HP_SYS_CLKRST.usb_device_ctrl0.reg_usb_device_apb_clk_en = 0; + USB_SERIAL_JTAG.mem_conf.usb_mem_pd = 1; + USB_SERIAL_JTAG.mem_conf.usb_mem_clk_en = 0; + CNNT_SYS_REG.sys_hp_usb_device_ctrl.sys_usb_device_48m_clk_en = 0; + } + } + + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_BROWN_OUT) || + (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) || + (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC)) { + LP_GPIO.clock_gate.clk_en = 0; + while (LP_GPIO.clock_gate.clk_en != 0) { + ; + } + LP_PERI_CLKRST.i2cmst_ctrl.lp_i2cmst_clk_en = 0; + LP_PERI_CLKRST.touch_ctrl.lp_touch_clk_en = 0; + LP_PERI_CLKRST.rng_ctrl.lp_rng_clk_en = 0; + LP_PERI_CLKRST.dm_ctrl.lp_dm_clk_en = 0; + if (config->disable_crypto_periph_clk) { + LP_APM.clock_gate.clk_en = 0; + } + } +} /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define clk_gate_ll_ref_25m_clk_en(...) do { \ @@ -125,29 +301,6 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_240m_clk_en(bool enable) _clk_gate_ll_ref_240m_clk_en(__VA_ARGS__); \ } while(0) -/** - * @brief Set the default clock gate configuration - */ -static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason) -{ - if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN) || - (rst_reason == RESET_REASON_SYS_BROWN_OUT) || (rst_reason == RESET_REASON_SYS_RWDT) || - (rst_reason == RESET_REASON_SYS_SUPER_WDT) || (rst_reason == RESET_REASON_CORE_SW) || - (rst_reason == RESET_REASON_CORE_MWDT0) || (rst_reason == RESET_REASON_CORE_MWDT1) || - (rst_reason == RESET_REASON_CORE_RWDT) || (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || - (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || (rst_reason == RESET_REASON_CORE_USB_JTAG) || - (rst_reason == RESET_REASON_CORE_USB_UART) - ) { - /* - * Default lcdcam_lcdcam_ctrl0: - * reg_lcdcam_clk_src_sel: 1 (BBPLL 120 MHz path, shared by LCD and CAM) - * reg_lcdcam_clk_div_num: 1 (divide by 2 → 60 MHz) - */ - HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 1; - HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_div_num = 1; - } -} - #ifdef __cplusplus } #endif diff --git a/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h b/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h index 7d11279f61e..87f8413add7 100644 --- a/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h +++ b/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -289,16 +289,22 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc * @param en true to enable, false to disable */ __attribute__((always_inline)) -static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en) +static inline void _mwdt_ll_enable_clock(timg_dev_t *hw, bool en) { - /* The clock always defaults to enabled on P4. - If we update to be able to enable/disable the clock then this function - needs to be protected with PERIPH_RCC_ATOMIC as it touches shared registers. - */ - (void)hw; - (void)en; + if (hw == &TIMERG0) { + HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_wdt_clk_en = en; + } else { + HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_wdt_clk_en = en; + } } +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define mwdt_ll_enable_clock(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _mwdt_ll_enable_clock(__VA_ARGS__); \ + } while(0) + #ifdef __cplusplus } #endif diff --git a/components/esp_system/port/soc/esp32s31/clk.c b/components/esp_system/port/soc/esp32s31/clk.c index dc14844cfa3..5655994b386 100644 --- a/components/esp_system/port/soc/esp32s31/clk.c +++ b/components/esp_system/port/soc/esp32s31/clk.c @@ -30,6 +30,7 @@ #include "esp_private/esp_pmu.h" #include "esp_rom_serial_output.h" #include "esp_rom_sys.h" +#include "hal/clk_gate_ll.h" /* Number of cycles to wait from the 32k XTAL oscillator to consider it running. * Larger values increase startup delay. Smaller values may cause false positive @@ -196,5 +197,36 @@ __attribute__((weak)) void esp_perip_clk_init(void) modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); #endif - periph_ll_clk_gate_set_default(esp_rom_get_reset_reason(0)); + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + periph_ll_clk_gate_config_t clk_gate_config = {0}; + +#if CONFIG_ESP_CONSOLE_UART_NUM != 0 + clk_gate_config.disable_uart0_clk = true; +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 1 + clk_gate_config.disable_uart1_clk = true; +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 2 + clk_gate_config.disable_uart2_clk = true; +#endif +#if CONFIG_ESP_CONSOLE_UART_NUM != 3 + clk_gate_config.disable_uart3_clk = true; +#endif +#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + clk_gate_config.disable_mspi_flash_clk = true; +#endif +#if CONFIG_SPIRAM + clk_gate_config.keep_psram_hp_clk = true; +#endif +#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD + clk_gate_config.disable_assist_clk = true; +#endif +#if !CONFIG_SECURE_ENABLE_TEE + clk_gate_config.disable_crypto_periph_clk = true; +#endif +#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED + clk_gate_config.disable_usb_serial_jtag = true; +#endif + + periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config); } diff --git a/components/freertos/port_systick.c b/components/freertos/port_systick.c index af877bcb15c..179d74b8390 100644 --- a/components/freertos/port_systick.c +++ b/components/freertos/port_systick.c @@ -75,6 +75,7 @@ void vSystimerSetup(void) PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_SYSTIMER_MODULE, ref_count) { if (ref_count == 0) { systimer_ll_enable_bus_clock(true); + systimer_ll_enable_sys_clock(true); systimer_ll_reset_register(); } } diff --git a/components/soc/esp32s31/ld/esp32s31.peripherals.ld b/components/soc/esp32s31/ld/esp32s31.peripherals.ld index 10f103077d7..1b763c48f27 100644 --- a/components/soc/esp32s31/ld/esp32s31.peripherals.ld +++ b/components/soc/esp32s31/ld/esp32s31.peripherals.ld @@ -60,7 +60,7 @@ PROVIDE ( SPIMEM2 = 0x20502000 ); PROVIDE ( SPIMEM3 = 0x20503000 ); PROVIDE ( TEE = 0x20504000 ); PROVIDE ( HP_APM = 0x20504400 ); -PROVIDE ( HP_MEM = 0x20504800 ); +PROVIDE ( HP_MEM_APM = 0x20504800 ); PROVIDE ( CPU_APM = 0x20504C00 ); PROVIDE ( HP_PERI0_PMS = 0x20505000 ); PROVIDE ( KEYMNG = 0x20506000 ); diff --git a/components/soc/esp32s31/register/soc/cpu_apm_struct.h b/components/soc/esp32s31/register/soc/cpu_apm_struct.h index f3d8b1fc48e..f0847b9646d 100644 --- a/components/soc/esp32s31/register/soc/cpu_apm_struct.h +++ b/components/soc/esp32s31/register/soc/cpu_apm_struct.h @@ -602,6 +602,7 @@ typedef struct { volatile cpu_apm_date_reg_t date; } cpu_apm_dev_t; +extern cpu_apm_dev_t CPU_APM; #ifndef __cplusplus _Static_assert(sizeof(cpu_apm_dev_t) == 0x400, "Invalid size of cpu_apm_dev_t structure"); diff --git a/components/soc/esp32s31/register/soc/hp_apm_struct.h b/components/soc/esp32s31/register/soc/hp_apm_struct.h index ce2ba679d92..96c3c63bec9 100644 --- a/components/soc/esp32s31/register/soc/hp_apm_struct.h +++ b/components/soc/esp32s31/register/soc/hp_apm_struct.h @@ -886,6 +886,7 @@ typedef struct { volatile hp_apm_date_reg_t date; } hp_apm_dev_t; +extern hp_apm_dev_t HP_APM; #ifndef __cplusplus _Static_assert(sizeof(hp_apm_dev_t) == 0x400, "Invalid size of hp_apm_dev_t structure"); diff --git a/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h b/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h index b1cbe9e0fd7..016005336a8 100644 --- a/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h +++ b/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h @@ -777,6 +777,7 @@ typedef struct { volatile hp_mem_apm_date_reg_t date; } hp_mem_apm_dev_t; +extern hp_mem_apm_dev_t HP_MEM_APM; #ifndef __cplusplus _Static_assert(sizeof(hp_mem_apm_dev_t) == 0x400, "Invalid size of hp_mem_apm_dev_t structure"); diff --git a/components/soc/esp32s31/register/soc/lp_apm_struct.h b/components/soc/esp32s31/register/soc/lp_apm_struct.h index 785511fa8d8..aa7e0425357 100644 --- a/components/soc/esp32s31/register/soc/lp_apm_struct.h +++ b/components/soc/esp32s31/register/soc/lp_apm_struct.h @@ -588,6 +588,7 @@ typedef struct { volatile lp_apm_date_reg_t date; } lp_apm_dev_t; +extern lp_apm_dev_t LP_APM; #ifndef __cplusplus _Static_assert(sizeof(lp_apm_dev_t) == 0x400, "Invalid size of lp_apm_dev_t structure"); diff --git a/components/soc/esp32s31/register/soc/lp_tee_struct.h b/components/soc/esp32s31/register/soc/lp_tee_struct.h index 9411439f2c6..00ca6be3f5d 100644 --- a/components/soc/esp32s31/register/soc/lp_tee_struct.h +++ b/components/soc/esp32s31/register/soc/lp_tee_struct.h @@ -236,6 +236,7 @@ typedef struct { volatile lp_tee_date_reg_t date; } lp_tee_dev_t; +extern lp_tee_dev_t LP_TEE; #ifndef __cplusplus _Static_assert(sizeof(lp_tee_dev_t) == 0x400, "Invalid size of lp_tee_dev_t structure"); diff --git a/components/soc/esp32s31/register/soc/tee_struct.h b/components/soc/esp32s31/register/soc/tee_struct.h index 89c611da183..ab74d830c10 100644 --- a/components/soc/esp32s31/register/soc/tee_struct.h +++ b/components/soc/esp32s31/register/soc/tee_struct.h @@ -180,6 +180,7 @@ typedef struct { volatile tee_date_reg_t date; } tee_dev_t; +extern tee_dev_t TEE; #ifndef __cplusplus _Static_assert(sizeof(tee_dev_t) == 0x400, "Invalid size of tee_dev_t structure");