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docs: Update CN translation for jtag-debugging

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Zhang Shuxian
2026-05-06 12:06:35 +08:00
parent 4440f45c2b
commit cdea8fc8ce
3 changed files with 9 additions and 9 deletions
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docs/en/api-guides/jtag-debugging/tips-and-quirks.rst
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@@ -129,7 +129,7 @@ What Is the Meaning of Debugger's Startup Commands?
On startup, debugger is issuing sequence of commands to reset the chip and halt it at specific line of code. This sequence (shown below) is user defined to pick up at most convenient/appropriate line and start debugging.
* ``set remote hardware-watchpoint-limit {IDF_TARGET_SOC_CPU_WATCHPOINTS_NUM}`` — Restrict GDB to using available hardware watchpoints supported by the chip, {IDF_TARGET_SOC_CPU_WATCHPOINTS_NUM} for {IDF_TARGET_NAME}. For more information see https://sourceware.org/gdb/onlinedocs/gdb/Remote-Configuration.html.
* ``mon reset halt`` — reset the chip and keep the CPUs halted. Target has to be reset to disable memory protection, which is required to enable FLASH support. If reset is not desirable, add an extra argument ``-c 'set ESP_FLASH_SIZE 0'`` to the start of the OpenOCD command line to disable FLASH support, see :ref:`jtag-debugging-tip-openocd-config-vars`. Alternatively, disable memory protection using the config option :ref:`CONFIG_ESP_SYSTEM_MEMPROT`.
* ``mon reset halt`` — reset the chip and keep the CPUs halted. Target has to be reset to disable memory protection, which is required to enable flash support. If reset is not desirable, add an extra argument ``-c 'set ESP_FLASH_SIZE 0'`` to the start of the OpenOCD command line to disable flash support, see :ref:`jtag-debugging-tip-openocd-config-vars`. Alternatively, disable memory protection using the config option :ref:`CONFIG_ESP_SYSTEM_MEMPROT`.
* ``maintenance flush register-cache`` — monitor (``mon``) command can not inform GDB that the target state has changed. GDB will assume that whatever stack the target had before ``mon reset halt`` will still be valid. In fact, after reset the target state will change, and executing ``maintenance flush register-cache`` is a way to force GDB to get new state from the target.
* ``thb app_main`` — insert a temporary hardware breakpoint at ``app_main``, put here another function name if required
* ``c`` — resume the program. It will then stop at breakpoint inserted at ``app_main``.
@@ -192,7 +192,7 @@ It is important to set the variable before including the ESP-specific configurat
* - ``ESP_RTOS``
- Set to ``none`` to disable RTOS support. In this case, thread list will not be available in GDB. Can be useful when debugging FreeRTOS itself, and stepping through the scheduler code.
* - ``ESP_FLASH_SIZE``
- Set to ``0`` to disable Flash breakpoints support. If set to ``0``, target will not be reset when GDB connects.
- Set to ``0`` to disable flash breakpoints support. If set to ``0``, target will not be reset when GDB connects.
* - ``ESP_SEMIHOST_BASEDIR``
- Set to the path (on the host) which will be the default directory for semihosting functions.
* - ``ESP_ONLYCPU``