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feat(riscv_trace): add trace support for ESP32-H2

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This commit is contained in:
Erhan Kurubas
2026-08-07 14:44:03 +02:00
parent 5e9000329a
commit cd89c2b22b
5 changed files with 179 additions and 2 deletions
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components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+8
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@@ -195,6 +195,10 @@ config SOC_APM_SUPPORTED
bool
default y
config SOC_RISCV_TRACE_SUPPORTED
bool
default y
config SOC_PMU_SUPPORTED
bool
default y
@@ -1250,3 +1254,7 @@ config SOC_BLE_PERIODIC_ADV_WITH_RESPONSE
config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
components/soc/esp32h2/include/soc/soc_caps.h
+4
View File
@@ -87,6 +87,7 @@
#define SOC_BOD_SUPPORTED 1
#define SOC_VBAT_SUPPORTED 1
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_RISCV_TRACE_SUPPORTED 1
#define SOC_PMU_SUPPORTED 1
#define SOC_RTC_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
@@ -530,3 +531,6 @@
/*------------------------------------- DEBUG CAPS -------------------------------------*/
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
components/soc/esp32h2/ld/esp32h2.peripherals.ld
+2
View File
@@ -67,3 +67,5 @@ PROVIDE ( LPPERI = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( LP_APM = 0x600B3800 );
PROVIDE ( OTP_DEBUG = 0x600B3C00 );
PROVIDE ( TRACE = 0x600C0000 );