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feat(phy): rename sleep modem state to sleep phy

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This commit is contained in:
cjin
2026-09-11 17:48:24 +08:00
parent a7121aef2c
commit cc9bbf1d2a
19 changed files with 100 additions and 98 deletions
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components/esp_hw_support/include/esp_private/esp_pau.h
+2
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@@ -26,11 +26,13 @@ extern "C" {
void pau_regdma_set_entry_link_addr(pau_regdma_link_addr_t *link_entries);
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
#if SOC_PM_PAU_REGDMA_LINK_MODEM
/**
* @brief Set the address of WiFi MAC REGDMA Link in modem state
* @param link_addr linked lists address
*/
void pau_regdma_set_modem_link_addr(void *link_addr);
#endif // SOC_PM_PAU_REGDMA_LINK_MODEM
/**
* @brief Software trigger regdma to perform modem link backup
components/esp_hw_support/include/esp_private/sleep_modem.h
+5 -5
View File
@@ -228,7 +228,7 @@ void sleep_modem_wifi_modem_state_deinit(void);
bool sleep_modem_wifi_modem_state_skip_light_sleep(void);
/**
* @brief Function to initialize and create the modem state phy link
* @brief Function to initialize and create the phy link
* @param link_head the pointer that point to the head of the created phy link
* @return
* - ESP_OK on success
@@ -236,24 +236,24 @@ bool sleep_modem_wifi_modem_state_skip_light_sleep(void);
* - ESP_ERR_INVALID_ARG if value is out of range
* - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
*/
esp_err_t sleep_modem_state_phy_link_init(void **link_head);
esp_err_t sleep_phy_link_init(void **link_head);
/**
* @brief Function to destroy and de-initialize modem state phy link
* @brief Function to destroy and de-initialize phy link
* @param link_head the phy link head will be destroyed
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if value is out of range
* - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
*/
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head);
esp_err_t sleep_phy_link_deinit(void *link_head);
/**
* @brief Function to configure PHY link regdma description at runtime
* @param link_context PHY link regdma description conteoxt pointer
* @param flags A bitmap to indicate the PHY link regdma description configuration flag
*/
void sleep_modem_state_phy_link_config(void *link_context, uint32_t flags);
void sleep_phy_link_config(void *link_context, uint32_t flags);
#endif
#ifdef __cplusplus
components/esp_hw_support/lowpower/CMakeLists.txt
+1 -1
View File
@@ -36,7 +36,7 @@ if((CONFIG_SOC_PM_SUPPORT_MODEM_PD OR CONFIG_SOC_PM_SUPPORT_TOP_PD) AND CONFIG_S
endif()
if(CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE)
list(APPEND srcs "port/${target}/sleep_modem_state.c")
list(APPEND srcs "port/${target}/sleep_phy.c")
endif()
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c → components/esp_hw_support/lowpower/port/esp32c5/sleep_phy.c
+44 -44
View File
@@ -37,77 +37,77 @@
static __attribute__((unused)) const char *TAG = "sleep";
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
typedef struct {
#define DESC_IDX_I2C_MST_ENA (0)
#define DESC_IDX_I2C_MST_DIS (1)
void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1];
} sleep_modem_state_phy_link_context_t;
} sleep_phy_link_context_t;
static esp_err_t sleep_modem_state_phy_wifi_init(void *arg)
static esp_err_t sleep_phy_retention_init(void *arg)
{
#define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
#define PHY_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_PHY))
static sleep_retention_entries_config_t wifi_modem_config[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
static sleep_retention_entries_config_t phy_modem_config[] = {
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = PHY_ENTRY() }, /* I2C MST enable */
/* PMU or software to trigger enable RF PHY */
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf3800000, 0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), .owner = WIFIMAC_ENTRY() },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
[5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = WIFIMAC_ENTRY() },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() },
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), .owner = WIFIMAC_ENTRY() },
[9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), .owner = WIFIMAC_ENTRY() },
[10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), .owner = PHY_ENTRY() }, /* BBPLL calibration enable */
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf3800000, 0xf3800000, 1, 0), .owner = PHY_ENTRY() },
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), .owner = PHY_ENTRY() },
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = PHY_ENTRY() },
[5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = PHY_ENTRY() },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0), .owner = PHY_ENTRY() },
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0), .owner = PHY_ENTRY() },
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), .owner = PHY_ENTRY() },
[9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), .owner = PHY_ENTRY() },
[10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), .owner = PHY_ENTRY() },
/* PMU to trigger enable RXBLOCK */
[11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), .owner = WIFIMAC_ENTRY() },
[11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), .owner = PHY_ENTRY() },
/* PMU or software to trigger disable RF PHY */
[12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
[13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), .owner = WIFIMAC_ENTRY() },
[14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1), .owner = WIFIMAC_ENTRY() },
[15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
[16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 1), .owner = WIFIMAC_ENTRY() },
[17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG, 0, 0x400000, 0, 1), .owner = WIFIMAC_ENTRY() },
[18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG, 0, 0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() },
[19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
[12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), .owner = PHY_ENTRY() },
[13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), .owner = PHY_ENTRY() },
[14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1), .owner = PHY_ENTRY() },
[15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 0, 1), .owner = PHY_ENTRY() },
[16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 0, 1), .owner = PHY_ENTRY() },
[17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG, 0, 0x400000, 0, 1), .owner = PHY_ENTRY() },
[18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG, 0, 0xf3800000, 0, 1), .owner = PHY_ENTRY() },
[19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), .owner = PHY_ENTRY() }, /* BBPLL calibration disable */
[20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
[20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), .owner = PHY_ENTRY() }, /* I2C MST disable */
/* PMU to trigger disable RXBLOCK */
[21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() },
[22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), .owner = WIFIMAC_ENTRY() },
[23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() },
[21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = PHY_ENTRY() },
[22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), .owner = PHY_ENTRY() },
[23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = PHY_ENTRY() },
[24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
[25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
[24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), .owner = PHY_ENTRY() },
[25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1), .owner = PHY_ENTRY() }
};
extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
wifi_modem_config[4].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
phy_modem_config[4].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
phy_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
esp_err_t err = sleep_retention_entries_create(phy_modem_config, ARRAY_SIZE(phy_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link");
return ESP_OK;
}
#endif
esp_err_t sleep_modem_state_phy_link_init(void **link_head)
esp_err_t sleep_phy_link_init(void **link_head)
{
esp_err_t err = ESP_OK;
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } };
#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_phy_retention_init, .arg = NULL } } };
err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
if (err == ESP_OK) {
err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
if (err == ESP_OK) {
const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x14) };
static DRAM_ATTR sleep_modem_state_phy_link_context_t phy_link_context;
static DRAM_ATTR sleep_phy_link_context_t phy_link_context;
for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
void *desc = sleep_retention_find_link_by_id(id_array[i]);
@@ -126,10 +126,10 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
return err;
}
void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t flags)
void IRAM_ATTR sleep_phy_link_config(void *link_context, uint32_t flags)
{
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
sleep_modem_state_phy_link_context_t *phy_link_context = (sleep_modem_state_phy_link_context_t *)link_context;
#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
sleep_phy_link_context_t *phy_link_context = (sleep_phy_link_context_t *)link_context;
if (flags & BIT(0)) {
regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
@@ -141,10 +141,10 @@ void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t fl
#endif
}
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
esp_err_t sleep_phy_link_deinit(void *link_head)
{
esp_err_t err = ESP_OK;
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
if (err == ESP_OK) {
sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c → components/esp_hw_support/lowpower/port/esp32c6/sleep_phy.c
+13 -13
View File
@@ -40,14 +40,14 @@ typedef struct {
#define DESC_IDX_I2C_MST_SEL (1)
#define DESC_IDX_I2C_MST_DIS (2)
void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1];
} sleep_modem_state_phy_link_context_t;
} sleep_phy_link_context_t;
esp_err_t sleep_modem_state_phy_link_init(void **link_head)
esp_err_t sleep_phy_link_init(void **link_head)
{
esp_err_t err = ESP_OK;
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
static regdma_link_config_t wifi_modem_config[] = {
#if SOC_PM_PAU_REGDMA_LINK_MODEM
static regdma_link_config_t phy_modem_config[] = {
[0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
[1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
@@ -100,12 +100,12 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
[38] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1)
};
extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
wifi_modem_config[7].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
wifi_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
phy_modem_config[7].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
phy_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
void *link = NULL;
for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
for (int i = ARRAY_SIZE(phy_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
void *next = regdma_link_init_safe(&phy_modem_config[i], false, 0, link);
if (next) {
link = next;
} else {
@@ -117,7 +117,7 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
pau_regdma_set_modem_link_addr(link);
const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x01), REGDMA_PHY_LINK(0x1b) };
static DRAM_ATTR sleep_modem_state_phy_link_context_t phy_link_context;
static DRAM_ATTR sleep_phy_link_context_t phy_link_context;
for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
void *desc = regdma_find_link_by_id(link, 0, id_array[i]);
@@ -136,9 +136,9 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
return err;
}
void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t flags)
void IRAM_ATTR sleep_phy_link_config(void *link_context, uint32_t flags)
{
sleep_modem_state_phy_link_context_t *phy_link_context = (sleep_modem_state_phy_link_context_t *)link_context;
sleep_phy_link_context_t *phy_link_context = (sleep_phy_link_context_t *)link_context;
if (flags & BIT(0)) {
regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
@@ -151,9 +151,9 @@ void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t fl
}
}
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
esp_err_t sleep_phy_link_deinit(void *link_head)
{
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
#if SOC_PM_PAU_REGDMA_LINK_MODEM
regdma_link_destroy(((sleep_modem_state_phy_link_context_t *)link_head)->link_head, 0);
#endif
return ESP_OK;
components/esp_hw_support/lowpower/port/esp32c61/sleep_modem_state.c → components/esp_hw_support/lowpower/port/esp32c61/sleep_phy.c
+14 -14
View File
@@ -37,14 +37,14 @@ typedef struct {
#define DESC_IDX_I2C_MST_ENA (0)
#define DESC_IDX_I2C_MST_DIS (1)
void *regdma_desc[DESC_IDX_I2C_MST_DIS + 1];
} sleep_modem_state_phy_link_context_t;
} sleep_phy_link_context_t;
esp_err_t sleep_modem_state_phy_link_init(void **link_head)
esp_err_t sleep_phy_link_init(void **link_head)
{
esp_err_t err = ESP_OK;
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
static regdma_link_config_t wifi_modem_config[] = {
#if SOC_PM_PAU_REGDMA_LINK_MODEM
static regdma_link_config_t phy_modem_config[] = {
[0] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), /* I2C MST enable */
/* PMU or software to trigger enable RF PHY */
@@ -71,7 +71,7 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
/* PMU or software to trigger disable RF PHY */
[16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1),
[17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1),
[18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 0, 1),
[18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1),
[19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 0, 1),
[20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
[21] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
@@ -95,12 +95,12 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
[35] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1)
};
extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
wifi_modem_config[4].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
wifi_modem_config[19].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
phy_modem_config[4].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
phy_modem_config[19].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
void *link = NULL;
for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
for (int i = ARRAY_SIZE(phy_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
void *next = regdma_link_init_safe(&phy_modem_config[i], false, 0, link);
if (next) {
link = next;
} else {
@@ -112,7 +112,7 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
pau_regdma_set_modem_link_addr(link);
const int id_array[] = { REGDMA_PHY_LINK(0x00), REGDMA_PHY_LINK(0x1a) };
static DRAM_ATTR sleep_modem_state_phy_link_context_t phy_link_context;
static DRAM_ATTR sleep_phy_link_context_t phy_link_context;
for (int i = 0; (err == ESP_OK) && (i < ARRAY_SIZE(phy_link_context.regdma_desc)); i++) {
void *desc = regdma_find_link_by_id(link, 0, id_array[i]);
@@ -131,9 +131,9 @@ esp_err_t sleep_modem_state_phy_link_init(void **link_head)
return err;
}
void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t flags)
void IRAM_ATTR sleep_phy_link_config(void *link_context, uint32_t flags)
{
sleep_modem_state_phy_link_context_t *phy_link_context = (sleep_modem_state_phy_link_context_t *)link_context;
sleep_phy_link_context_t *phy_link_context = (sleep_phy_link_context_t *)link_context;
if (flags & BIT(0)) {
regdma_link_set_skip_flag(phy_link_context->regdma_desc[DESC_IDX_I2C_MST_ENA], true, true);
@@ -144,9 +144,9 @@ void IRAM_ATTR sleep_modem_state_phy_link_config(void *link_context, uint32_t fl
}
}
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
esp_err_t sleep_phy_link_deinit(void *link_head)
{
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
#if SOC_PM_PAU_REGDMA_LINK_MODEM
regdma_link_destroy(((sleep_modem_state_phy_link_context_t *)link_head)->link_head, 0);
#endif
return ESP_OK;
components/esp_hw_support/port/pau_regdma.c
+1 -1
View File
@@ -69,7 +69,7 @@ void pau_regdma_set_entry_link_addr(pau_regdma_link_addr_t *link_entries)
}
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
#if SOC_PM_PAU_REGDMA_LINK_MODEM
void pau_regdma_set_modem_link_addr(void *link_addr)
{
pau_hal_set_regdma_modem_link_addr(PAU_instance()->hal, link_addr);
components/esp_hw_support/sleep_modem.c
+4 -4
View File
@@ -153,7 +153,7 @@ esp_err_t sleep_modem_wifi_modem_state_init(void)
void *link = NULL;
if (s_sleep_modem.wifi.phy_link == NULL) {
err = sleep_modem_state_phy_link_init(&link);
err = sleep_phy_link_init(&link);
if (err == ESP_OK) {
s_sleep_modem.wifi.phy_link = link;
s_sleep_modem.wifi.flags = 0;
@@ -165,7 +165,7 @@ esp_err_t sleep_modem_wifi_modem_state_init(void)
__attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void)
{
if (s_sleep_modem.wifi.phy_link) {
sleep_modem_state_phy_link_deinit(s_sleep_modem.wifi.phy_link);
sleep_phy_link_deinit(s_sleep_modem.wifi.phy_link);
s_sleep_modem.wifi.phy_link = NULL;
s_sleep_modem.wifi.flags = 0;
}
@@ -173,9 +173,9 @@ __attribute__((unused)) void sleep_modem_wifi_modem_state_deinit(void)
void IRAM_ATTR sleep_modem_wifi_do_phy_retention(bool restore, bool wifimac_link_is_sel)
{
sleep_modem_state_phy_link_config(s_sleep_modem.wifi.phy_link, 1);
sleep_phy_link_config(s_sleep_modem.wifi.phy_link, 1);
sleep_retention_do_phy_retention(!restore, wifimac_link_is_sel);
sleep_modem_state_phy_link_config(s_sleep_modem.wifi.phy_link, 0);
sleep_phy_link_config(s_sleep_modem.wifi.phy_link, 0);
if (!restore) {
s_sleep_modem.wifi.modem_state_phy_done = 1;
}
components/esp_phy/src/phy_init.c
+3 -3
View File
@@ -68,7 +68,7 @@ extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
extern void pm_mac_modem_clear_rf_power_state(void);
extern bool pm_mac_modem_rf_already_enabled(void);
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY
extern bool pm_get_wifimac_regdma_link_selection(void);
#endif
#endif
@@ -352,7 +352,7 @@ void esp_phy_enable(esp_phy_modem_t modem)
bool wifimac_link_is_sel = false;
if (!pm_mac_modem_rf_already_enabled()) {
if (sleep_modem_wifi_modem_state_enabled() && sleep_modem_wifi_modem_link_done()) {
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
/*
* A race exists between SoC wakeup and modem state sleep. After modem initiates sleep,
* SoC may wake up before REGDMA completes RF close, leaving mac_modem_sleep_flag uncleared
@@ -432,7 +432,7 @@ void esp_phy_disable(esp_phy_modem_t modem)
pm_mac_modem_clear_rf_power_state();
if (sleep_modem_wifi_modem_state_enabled()) {
bool wifimac_link_is_sel = false;
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
#if SOC_PM_PAU_REGDMA_LINK_IDX_PHY && SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
wifimac_link_is_sel = pm_get_wifimac_regdma_link_selection();
#endif
sleep_modem_wifi_do_phy_retention(false, wifimac_link_is_sel);
components/hal/esp32c5/pau_hal.c
+1 -1
View File
@@ -18,7 +18,7 @@ void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_
void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
{
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
pau_ll_select_regdma_entry_link(hal->dev, SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC);
pau_ll_select_regdma_entry_link(hal->dev, SOC_PM_PAU_REGDMA_LINK_IDX_PHY);
pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore);
pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev);
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
components/hal/include/hal/pau_hal.h
+1 -1
View File
@@ -38,7 +38,7 @@ typedef struct {
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr);
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
#if SOC_PM_PAU_REGDMA_LINK_MODEM
/**
* @brief Set regdma modem link address
*
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4 -4
View File
@@ -1739,10 +1739,6 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
bool
default y
config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
int
default 4
config SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY
bool
default y
@@ -1751,6 +1747,10 @@ config SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND
bool
default y
config SOC_PM_PAU_REGDMA_LINK_IDX_PHY
int
default 4
config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1 -1
View File
@@ -668,10 +668,10 @@
#define SOC_PM_PAU_LINK_NUM (5)
#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
#define SOC_PM_PAU_REGDMA_COMMON_PHY_LINK_ENTRY (1)
/** Workaround: software-triggered modem PHY retention uses dedicated WiFi MAC REGDMA, not entry link_sel */
#define SOC_PM_PAU_REGDMA_MODEM_WIFIMAC_WORKAROUND (1)
#define SOC_PM_PAU_REGDMA_LINK_IDX_PHY (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -1503,7 +1503,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
bool
default y
config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
config SOC_PM_PAU_REGDMA_LINK_MODEM
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+1 -1
View File
@@ -585,7 +585,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC (1)
#define SOC_PM_PAU_REGDMA_LINK_MODEM (1)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)
#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1)
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -1223,7 +1223,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
bool
default y
config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
config SOC_PM_PAU_REGDMA_LINK_MODEM
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
+1 -1
View File
@@ -489,7 +489,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC (1)
#define SOC_PM_PAU_REGDMA_LINK_MODEM (1)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)
#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED (1)
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -1459,7 +1459,7 @@ config SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR
bool
default y
config SOC_PM_PAU_REGDMA_LINK_WIFIMAC
config SOC_PM_PAU_REGDMA_LINK_MODEM
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+1 -1
View File
@@ -583,7 +583,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
#define SOC_PM_PAU_REGDMA_LINK_WIFIMAC (1)
#define SOC_PM_PAU_REGDMA_LINK_MODEM (1)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)