From e28ff721542b1baec2aa24a036ce9248bf8da784 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 5 Nov 2025 16:18:16 +0800 Subject: [PATCH 1/2] feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 --- .../esp_driver_gpio/include/driver/gpio.h | 16 +++++---- components/esp_driver_gpio/src/gpio.c | 6 ++-- .../test_apps/gpio/main/test_gpio.c | 35 +++++++++++++++---- .../test_apps/gpio/main/test_gpio.h | 1 + .../test_apps/gpio/main/test_rtcio.c | 6 ++-- .../test_apps/gpio/main/test_rtcio.h | 1 + .../include/esp_private/esp_sleep_internal.h | 2 +- .../port/esp32p4/private_include/pmu_param.h | 15 ++++++++ components/esp_hw_support/sleep_gpio.c | 4 +-- components/esp_hw_support/sleep_modes.c | 2 +- components/hal/esp32p4/include/hal/gpio_ll.h | 25 +++++++++++++ .../hal/esp32p4/include/hal/rtc_io_ll.h | 10 ++++++ components/hal/include/hal/gpio_hal.h | 4 +-- .../soc/esp32/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32/include/soc/soc_caps.h | 3 -- .../esp32c2/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32c2/include/soc/soc_caps.h | 3 -- .../esp32c3/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32c3/include/soc/soc_caps.h | 3 -- .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32c5/include/soc/soc_caps.h | 2 -- .../esp32c6/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32c6/include/soc/soc_caps.h | 2 -- .../esp32c61/include/soc/Kconfig.soc_caps.in | 4 --- .../soc/esp32c61/include/soc/soc_caps.h | 2 -- .../esp32h2/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32h2/include/soc/soc_caps.h | 2 -- .../esp32h21/include/soc/Kconfig.soc_caps.in | 4 --- .../soc/esp32h21/include/soc/soc_caps.h | 2 -- .../esp32p4/include/soc/Kconfig.soc_caps.in | 12 ++++--- components/soc/esp32p4/include/soc/soc_caps.h | 8 +++-- .../register/hw_ver3/soc/hp_system_struct.h | 34 +----------------- .../register/hw_ver3/soc/lp_iomux_struct.h | 18 +--------- .../esp32s2/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32s2/include/soc/soc_caps.h | 3 -- .../esp32s3/include/soc/Kconfig.soc_caps.in | 4 --- components/soc/esp32s3/include/soc/soc_caps.h | 3 -- 37 files changed, 117 insertions(+), 147 deletions(-) diff --git a/components/esp_driver_gpio/include/driver/gpio.h b/components/esp_driver_gpio/include/driver/gpio.h index 7e375e2cb15..7cbb8b01424 100644 --- a/components/esp_driver_gpio/include/driver/gpio.h +++ b/components/esp_driver_gpio/include/driver/gpio.h @@ -416,23 +416,25 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren * signal or the IO MUX/GPIO configuration is modified (including input enable, output enable, output value, * function, and drive strength values). This function can be used to retain the state of GPIOs when the power * domain of where GPIO/IOMUX belongs to becomes off. For example, chip or system is reset (e.g. watchdog - * time-out, deep-sleep events are triggered), or peripheral power-down in light-sleep. + * time-out, Deep-sleep events are triggered), or peripheral power-down in Light-sleep. * * This function works in both input and output modes, and only applicable to output-capable GPIOs. * If this function is enabled: * in output mode: the output level of the GPIO will be locked and can not be changed. * in input mode: the input read value can still reflect the changes of the input signal. * + * Power down or call `gpio_hold_dis` will disable this function. + * * Please be aware that, * - * On ESP32P4, the states of IOs can not be hold after waking up from Deep-sleep. + * 1. USB pads cannot hold at low level after waking up from Deep-sleep. The USB related registers are reset, so the USB pull-up is back. * - * Additionally, on ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep. + * 2. For ESP32-P4 rev < 3.0, the states of IOs can not be hold after waking up from Deep-sleep. + * + * 3. For ESP32/S2/C3/S3/C2, this function cannot be used to hold the state of a digital GPIO during Deep-sleep. * Even if this function is enabled, the digital GPIO will be reset to its default state when the chip wakes up from * Deep-sleep. If you want to hold the state of a digital GPIO during Deep-sleep, please call `gpio_deep_sleep_hold_en`. * - * Power down or call `gpio_hold_dis` will disable this function. - * * @param gpio_num GPIO number, only support output-capable GPIOs * * @return @@ -460,7 +462,7 @@ esp_err_t gpio_hold_en(gpio_num_t gpio_num); */ esp_err_t gpio_hold_dis(gpio_num_t gpio_num); -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Enable all digital gpio pads hold function during Deep-sleep. * @@ -484,7 +486,7 @@ void gpio_deep_sleep_hold_en(void); * @brief Disable all digital gpio pads hold function during Deep-sleep. */ void gpio_deep_sleep_hold_dis(void); -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP #if SOC_GPIO_SUPPORT_FORCE_HOLD /** diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c index 9c494a2631f..df11fb96a99 100644 --- a/components/esp_driver_gpio/src/gpio.c +++ b/components/esp_driver_gpio/src/gpio.c @@ -8,13 +8,13 @@ #include "esp_err.h" #include "freertos/FreeRTOS.h" #include "esp_heap_caps.h" +#include "sdkconfig.h" #include "driver/gpio.h" #include "driver/rtc_io.h" #include "soc/interrupts.h" #if !CONFIG_FREERTOS_UNICORE #include "esp_ipc.h" #endif - #include "soc/soc_caps.h" #include "soc/gpio_periph.h" #include "esp_log.h" @@ -775,7 +775,7 @@ esp_err_t gpio_hold_dis(gpio_num_t gpio_num) return ret; } -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP void gpio_deep_sleep_hold_en(void) { portENTER_CRITICAL(&gpio_context.gpio_spinlock); @@ -789,7 +789,7 @@ void gpio_deep_sleep_hold_dis(void) gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal); portEXIT_CRITICAL(&gpio_context.gpio_spinlock); } -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP #if SOC_GPIO_SUPPORT_FORCE_HOLD esp_err_t IRAM_ATTR gpio_force_hold_all() diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c index f4e249a25eb..286720482de 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c @@ -884,7 +884,7 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]") } #endif -#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#if SOC_DEEP_SLEEP_SUPPORTED // Pick one digital IO for each target to test is enough static void gpio_deep_sleep_hold_test_first_stage(void) { @@ -902,7 +902,9 @@ static void gpio_deep_sleep_hold_test_first_stage(void) .pull_up_en = GPIO_PULLUP_DISABLE, }; TEST_ESP_OK(gpio_config(&io_conf)); - TEST_ESP_OK(gpio_set_level(io_num, 0)); + + const bool initial_level = gpio_get_level(io_num); + TEST_ESP_OK(gpio_set_level(io_num, !initial_level)); // Enable global persistence TEST_ESP_OK(gpio_hold_en(io_num)); @@ -911,6 +913,10 @@ static void gpio_deep_sleep_hold_test_first_stage(void) // Extra step is required, so that all digital IOs can automatically get held when entering Deep-sleep gpio_deep_sleep_hold_en(); #endif + vTaskDelay(pdMS_TO_TICKS(200)); + TEST_ESP_OK(gpio_set_level(io_num, initial_level)); + TEST_ASSERT_EQUAL_INT(!initial_level, gpio_get_level(io_num)); + vTaskDelay(pdMS_TO_TICKS(200)); esp_deep_sleep_start(); } @@ -921,16 +927,31 @@ static void gpio_deep_sleep_hold_test_second_stage(void) // Check reset reason is waking up from deepsleep TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason()); - // Pin should stay at low level after the deep sleep - TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num)); +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399 + bool level = gpio_get_level(io_num); // Set level should not take effect since hold is still active (and the INPUT_OUTPUT mode should still be held) - TEST_ESP_OK(gpio_set_level(io_num, 1)); - TEST_ASSERT_EQUAL_INT(0, gpio_get_level(io_num)); + TEST_ESP_OK(gpio_set_level(io_num, !level)); + TEST_ASSERT_EQUAL_INT(level, gpio_get_level(io_num)); +#endif #if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP gpio_deep_sleep_hold_dis(); #endif TEST_ESP_OK(gpio_hold_dis(io_num)); + + gpio_config_t io_conf = { + .intr_type = GPIO_INTR_DISABLE, + .mode = GPIO_MODE_INPUT_OUTPUT, + .pin_bit_mask = (1ULL << io_num), + .pull_down_en = GPIO_PULLDOWN_DISABLE, + .pull_up_en = GPIO_PULLUP_DISABLE, + }; + TEST_ESP_OK(gpio_config(&io_conf)); + +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399 + // Check that the hold level after wakeup is the level before entering deep sleep + TEST_ASSERT_EQUAL_INT(!level, gpio_get_level(io_num)); +#endif } /* @@ -942,4 +963,4 @@ static void gpio_deep_sleep_hold_test_second_stage(void) TEST_CASE_MULTIPLE_STAGES("GPIO_deep_sleep_output_hold_test", "[gpio]", gpio_deep_sleep_hold_test_first_stage, gpio_deep_sleep_hold_test_second_stage) -#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#endif // SOC_DEEP_SLEEP_SUPPORTED diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h index 2000b19520d..3caa9c2001f 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.h @@ -39,6 +39,7 @@ extern "C" { #define TEST_GPIO_EXT_IN_IO (3) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC250_IDX) +#define TEST_GPIO_DEEP_SLEEP_HOLD_PIN (28) #elif CONFIG_IDF_TARGET_ESP32H2 #define TEST_GPIO_EXT_OUT_IO (2) #define TEST_GPIO_EXT_IN_IO (3) diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c index 3a8e2697c87..fd0735b3e88 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c @@ -278,7 +278,7 @@ TEST_CASE("RTCIO_interrupt_test", "[rtcio]") #endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0) #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED -#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#if SOC_DEEP_SLEEP_SUPPORTED // It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep // Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin // The default configuration of these pads is low level @@ -311,8 +311,10 @@ static void rtcio_deep_sleep_hold_test_second_stage(void) int io_num = s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX]; // Check reset reason is waking up from deepsleep TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason()); +#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 // DIG-399 // Pin should stay at high level after the deep sleep TEST_ASSERT_EQUAL_INT(1, gpio_get_level(io_num)); +#endif gpio_hold_dis(io_num); } @@ -326,4 +328,4 @@ static void rtcio_deep_sleep_hold_test_second_stage(void) TEST_CASE_MULTIPLE_STAGES("RTCIO_deep_sleep_output_hold_test", "[rtcio]", rtcio_deep_sleep_hold_test_first_stage, rtcio_deep_sleep_hold_test_second_stage) -#endif // SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP +#endif // SOC_DEEP_SLEEP_SUPPORTED diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h index e72580f8976..5b07231356a 100644 --- a/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h +++ b/components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h @@ -162,6 +162,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = { GPIO_NUM_15, //GPIO15 }; #define TEST_RTCIO_INTR_PIN_INDEX 2 // IO2 +#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5 #elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5 // Has no input-only rtcio pins, all pins support pull-up/down #define RTCIO_SUPPORT_PU_PD(num) 1 diff --git a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h index e9c5a569fea..f424f7d903a 100644 --- a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h +++ b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h @@ -97,7 +97,7 @@ esp_err_t esp_sleep_acquire_lp_use_xtal(void); esp_err_t esp_sleep_release_lp_use_xtal(void); #endif -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Isolate all digital IOs except those that are held during deep sleep * diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h index c7f61b07232..ca28b67104f 100644 --- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h @@ -11,6 +11,7 @@ #include #include "soc/pmu_struct.h" #include "hal/pmu_hal.h" +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { @@ -330,6 +331,7 @@ typedef struct { } pmu_sleep_digital_config_t; +#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3 #define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \ .syscntl = { \ .dig_pad_slp_sel = 0, \ @@ -343,6 +345,19 @@ typedef struct { .lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ } \ } +#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3 +#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \ + .syscntl = { \ + .dig_pad_slp_sel = 0, \ + } \ +} + +#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \ + .syscntl = { \ + .dig_pad_slp_sel = 0, \ + } \ +} +#endif typedef struct { struct { diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index 78d6b652419..0ac1dd67cfe 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -170,7 +170,7 @@ void esp_sleep_enable_gpio_switch(bool enable) } } -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP IRAM_ATTR void esp_sleep_isolate_digital_gpio(void) { gpio_hal_context_t gpio_hal = { @@ -225,7 +225,7 @@ IRAM_ATTR void esp_sleep_isolate_digital_gpio(void) } } } -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP #if SOC_DEEP_SLEEP_SUPPORTED void esp_deep_sleep_wakeup_io_reset(void) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 6730ae3838f..e4a36e8b57f 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -905,7 +905,7 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint } #endif if (deep_sleep) { -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP esp_sleep_isolate_digital_gpio(); #endif diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index e5508f6f8b5..57402074854 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -22,6 +22,7 @@ #include "soc/io_mux_reg.h" #include "soc/io_mux_struct.h" #include "soc/hp_system_struct.h" +#include "soc/lp_system_struct.h" #include "soc/lp_iomux_struct.h" #include "soc/hp_sys_clkrst_struct.h" #include "soc/pmu_struct.h" @@ -489,6 +490,13 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu __attribute__((always_inline)) static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + if (gpio_num < 32) { + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= (1 << gpio_num); + } else { + LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 |= (1 << (gpio_num - 32)); + } +#else uint64_t bit_mask = 1ULL << gpio_num; if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { // GPIO 0-15 @@ -504,6 +512,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high |= (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } +#endif } /** @@ -515,6 +524,13 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) __attribute__((always_inline)) static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + if (gpio_num < 32) { + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~(1 << gpio_num); + } else { + LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 &= ~(1 << (gpio_num - 32)); + } +#else uint64_t bit_mask = 1ULL << gpio_num; if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) { // GPIO 0-15 @@ -530,6 +546,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high &= ~(bit_mask >> (32 + SOC_RTCIO_PIN_COUNT)); } } +#endif } /** @@ -552,6 +569,13 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) // GPIO 0-15 abort(); } else { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + if (gpio_num < 32) { + return !!(LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 & (1 << gpio_num)); + } else { + return !!(LP_SYS.pad_rtc_hold_ctrl1.pad_rtc_hold_ctrl1 & (1 << (gpio_num - 32))); + } +#else if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) { // GPIO 16-47 return !!(HP_SYSTEM.gpio_o_hold_ctrl0.reg_gpio_0_hold_low & (bit_mask >> SOC_RTCIO_PIN_COUNT)); @@ -559,6 +583,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num) // GPIO 48-54 return !!(HP_SYSTEM.gpio_o_hold_ctrl1.reg_gpio_0_hold_high & (bit_mask >> (32 + SOC_RTCIO_PIN_COUNT))); } +#endif } } diff --git a/components/hal/esp32p4/include/hal/rtc_io_ll.h b/components/hal/esp32p4/include/hal/rtc_io_ll.h index a46be6823d1..2424fe20e77 100644 --- a/components/hal/esp32p4/include/hal/rtc_io_ll.h +++ b/components/hal/esp32p4/include/hal/rtc_io_ll.h @@ -18,10 +18,12 @@ #include "soc/lp_gpio_struct.h" #include "soc/lp_iomux_struct.h" #include "soc/lp_gpio_sig_map.h" +#include "soc/lp_system_struct.h" #include "soc/pmu_struct.h" #include "hal/gpio_types.h" #include "hal/misc.h" #include "hal/assert.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -312,9 +314,13 @@ static inline bool rtcio_ll_is_pulldown_enabled(int rtcio_num) */ static inline void rtcio_ll_force_hold_enable(int rtcio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 |= BIT(rtcio_num); +#else uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold); hold_mask |= BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask); +#endif } /** @@ -325,9 +331,13 @@ static inline void rtcio_ll_force_hold_enable(int rtcio_num) */ static inline void rtcio_ll_force_hold_disable(int rtcio_num) { +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + LP_SYS.pad_rtc_hold_ctrl0.pad_rtc_hold_ctrl0 &= ~BIT(rtcio_num); +#else uint32_t hold_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold); hold_mask &= ~BIT(rtcio_num); HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hold, reg_lp_gpio_hold, hold_mask); +#endif } /** diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index e3adeb43268..f9e949ca019 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -323,7 +323,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); */ #define gpio_hal_is_digital_io_hold(hal, gpio_num) gpio_ll_is_digital_io_hold((hal)->dev, gpio_num) -#if SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Enable all digital gpio pad hold function during Deep-sleep. * @@ -354,7 +354,7 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num); * - false deep sleep hold is disabled */ #define gpio_hal_deep_sleep_hold_is_en(hal) gpio_ll_deep_sleep_hold_is_en((hal)->dev) -#endif //SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP && !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP +#endif //!SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP /** * @brief Set pad input to a peripheral signal through the IOMUX. diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index fd0d76b0992..21355136a4f 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -355,10 +355,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 8040f364fb7..5d9b02f4d9f 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -199,9 +199,6 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32 has 2 I2C #define SOC_I2C_NUM (2U) diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 39812894908..a79fd8fa486 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -323,10 +323,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_I2C_NUM int default 1 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index f8b7b24cf5d..701ee2c5ea0 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -149,9 +149,6 @@ #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-C2 has 1 I2C #define SOC_I2C_NUM (1U) diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 7d6b01b69c8..4472fc985b0 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -419,10 +419,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_I2C_NUM int default 1 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 9dcbeae032b..d25c7c661ea 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -188,9 +188,6 @@ #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-C3 has 1 I2C #define SOC_I2C_NUM (1U) diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 494f4098938..0c36c652073 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -579,10 +579,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 16209316e63..1b8bdd4b4bf 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -237,8 +237,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 4e58fe0b164..f393b198d6c 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -511,10 +511,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 89768a54e5e..a64d07dfdb1 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -215,8 +215,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 7c3e574238d..55a0f500c52 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -455,10 +455,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index e156c5daefd..41ea7882d0c 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -196,8 +196,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// "LP"_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index bc81eaf985f..2bec2242c6d 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -531,10 +531,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index d46bef6e2da..1c00ce0f0cf 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -240,8 +240,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 6bdcec69a75..1878f56aec7 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -387,10 +387,6 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 1475416a83b..471f8c01c81 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -220,8 +220,6 @@ // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// LP_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) // Support to hold a single digital I/O when the digital domain is powered off #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 62949459747..ad552e26714 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -695,6 +695,14 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x007FFFFFFFFF0000 +config SOC_GPIO_SUPPORT_FORCE_HOLD + bool + default y + +config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP + bool + default y + config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX bool default y @@ -715,10 +723,6 @@ config SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH int default 16 -config SOC_GPIO_SUPPORT_FORCE_HOLD - bool - default y - config SOC_RTCIO_PIN_COUNT int default 16 diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 6913444bc8f..cee0a5c85d2 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -265,6 +265,11 @@ // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL +// Support to force hold all IOs +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// Support to hold a single digital I/O when the digital domain is powered off +#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) // Supported only on ESP32P4 rev >= 3.0 (see DIG-399) + // The Clock Out signal is route to the pin by GPIO matrix #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (2) @@ -273,9 +278,6 @@ #define SOC_DEBUG_PROBE_NUM_UNIT (1U) // Number of debug probe units #define SOC_DEBUG_PROBE_MAX_OUTPUT_WIDTH (16) // Maximum width of the debug probe output in each unit -// Support to force hold all IOs -#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) - /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 16 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, diff --git a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h index 86a980f8e0e..8e62f2bec84 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/hp_system_struct.h @@ -413,37 +413,6 @@ typedef union { } hp_crypto_ctrl_reg_t; -/** Group: HP GPIO O HOLD CTRL0 REG */ -/** Type of gpio_o_hold_ctrl0 register - * NA - */ -typedef union { - struct { - /** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0; - * hold control for gpio47~16 - */ - uint32_t reg_gpio_0_hold_low:32; - }; - uint32_t val; -} hp_gpio_o_hold_ctrl0_reg_t; - - -/** Group: HP GPIO O HOLD CTRL1 REG */ -/** Type of gpio_o_hold_ctrl1 register - * NA - */ -typedef union { - struct { - /** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0; - * hold control for gpio56~48 - */ - uint32_t reg_gpio_0_hold_high:9; - uint32_t reserved_9:23; - }; - uint32_t val; -} hp_gpio_o_hold_ctrl1_reg_t; - - /** Group: HP SYS RDN ECO CS REG */ /** Type of sys_rdn_eco_cs register * NA @@ -2149,8 +2118,7 @@ typedef struct hp_system_dev_t { volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st; uint32_t reserved_068[2]; volatile hp_crypto_ctrl_reg_t crypto_ctrl; - volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0; - volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1; + uint32_t reserved_074[2]; volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs; volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en; volatile hp_l2_mem_subsize_reg_t l2_mem_subsize; diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h index 740839aecdc..c445ffbd166 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_iomux_struct.h @@ -114,22 +114,6 @@ typedef union { } lp_iomux_ext_wakeup0_sel_reg_t; -/** Group: lp_pad_hold */ -/** Type of lp_pad_hold register - * Reserved - */ -typedef union { - struct { - /** reg_lp_gpio_hold : R/W; bitpos: [15:0]; default: 0; - * Reserved - */ - uint32_t reg_lp_gpio_hold:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} lp_iomux_lp_pad_hold_reg_t; - - /** Group: lp_pad_hys */ /** Type of lp_pad_hys register * Reserved @@ -151,7 +135,7 @@ typedef struct lp_iomux_dev_t { volatile lp_iomux_ver_date_reg_t ver_date; volatile lp_iomux_pad_reg_t pad[16]; volatile lp_iomux_ext_wakeup0_sel_reg_t ext_wakeup0_sel; - volatile lp_iomux_lp_pad_hold_reg_t lp_pad_hold; + uint32_t reserved_04c; volatile lp_iomux_lp_pad_hys_reg_t lp_pad_hys; } lp_iomux_dev_t; diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 30ed2429973..186d2ae2b65 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -415,10 +415,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_DEDIC_GPIO_HAS_INTERRUPT bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index dbacc847a0c..6376fe2a58b 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -190,9 +190,6 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ #define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */ diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 805a2dfc88c..1af3e5af9ac 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -479,10 +479,6 @@ config SOC_GPIO_CLOCKOUT_CHANNEL_NUM int default 3 -config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP - bool - default y - config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index dd2ed30876c..bb599f03817 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -201,9 +201,6 @@ #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) -// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up -#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1) - /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32-S3 has 2 I2C #define SOC_I2C_NUM (2U) From 05c2486d8b48e3c4d6350c241bc2d9083ebdfb4a Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Tue, 11 Nov 2025 17:02:32 +0800 Subject: [PATCH 2/2] fix(clk): 400MHz CPU should still be selectable on ESP32-P4 less than rev3 --- components/esp_system/port/CMakeLists.txt | 4 ++++ components/esp_system/port/soc/esp32p4/Kconfig.cpu | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/components/esp_system/port/CMakeLists.txt b/components/esp_system/port/CMakeLists.txt index d3adc03954a..0aa682d0561 100644 --- a/components/esp_system/port/CMakeLists.txt +++ b/components/esp_system/port/CMakeLists.txt @@ -6,6 +6,10 @@ endif() target_include_directories(${COMPONENT_LIB} PRIVATE ${INCLUDE_FILES} include/private) +if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_400) + message(WARNING "400 MHz CPU frequency is not guaranteed to work on all chips with revision prior to rev 3!") +endif() + set(srcs "cpu_start.c" "panic_handler.c" "esp_system_chip.c") if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP) diff --git a/components/esp_system/port/soc/esp32p4/Kconfig.cpu b/components/esp_system/port/soc/esp32p4/Kconfig.cpu index 47064a383ac..d88464cc994 100644 --- a/components/esp_system/port/soc/esp32p4/Kconfig.cpu +++ b/components/esp_system/port/soc/esp32p4/Kconfig.cpu @@ -14,7 +14,6 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ depends on ESP32P4_SELECTS_REV_LESS_V3 config ESP_DEFAULT_CPU_FREQ_MHZ_400 bool "400 MHz" - depends on !ESP32P4_SELECTS_REV_LESS_V3 endchoice config ESP_DEFAULT_CPU_FREQ_MHZ