diff --git a/components/esp_driver_dma/esp32h4/gdma_retention.c b/components/esp_driver_dma/esp32h4/gdma_retention.c index 79a265ea5ae..27e72860fca 100644 --- a/components/esp_driver_dma/esp32h4/gdma_retention.c +++ b/components/esp_driver_dma/esp32h4/gdma_retention.c @@ -30,7 +30,7 @@ static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x7 static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ G0P0_RETENTION_REGS_CNT_0, 0, 0, \ g0p0_regs_map0[0], g0p0_regs_map0[1], \ @@ -38,7 +38,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ G0P0_RETENTION_REGS_CNT_1, 0, 0, \ g0p0_regs_map1[0], g0p0_regs_map1[1], \ @@ -75,7 +75,7 @@ static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ G0P1_RETENTION_REGS_CNT_0, 0, 0, \ g0p1_regs_map0[0], g0p1_regs_map0[1], \ @@ -83,7 +83,7 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ G0P1_RETENTION_REGS_CNT_1, 0, 0, \ g0p1_regs_map1[0], g0p1_regs_map1[1], \ @@ -91,7 +91,7 @@ static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x02), \ G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ G0P1_RETENTION_REGS_CNT_2, 0, 0, \ g0p1_regs_map2[0], g0p1_regs_map2[1], \ @@ -127,7 +127,7 @@ static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ G0P2_RETENTION_REGS_CNT_0, 0, 0, \ g0p2_regs_map0[0], g0p2_regs_map0[1], \ @@ -135,7 +135,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ G0P2_RETENTION_REGS_CNT_1, 0, 0, \ g0p2_regs_map1[0], g0p2_regs_map1[1], \ @@ -143,7 +143,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x02), \ G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ G0P2_RETENTION_REGS_CNT_2, 0, 0, \ g0p2_regs_map2[0], g0p2_regs_map2[1], \ @@ -179,7 +179,7 @@ static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p3_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ G0P3_RETENTION_REGS_CNT_0, 0, 0, \ g0p3_regs_map0[0], g0p3_regs_map0[1], \ @@ -187,7 +187,7 @@ static const regdma_entries_config_t gdma_g0p3_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ G0P3_RETENTION_REGS_CNT_1, 0, 0, \ g0p3_regs_map1[0], g0p3_regs_map1[1], \ @@ -195,7 +195,7 @@ static const regdma_entries_config_t gdma_g0p3_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x02), \ G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ G0P3_RETENTION_REGS_CNT_2, 0, 0, \ g0p3_regs_map2[0], g0p3_regs_map2[1], \ @@ -227,7 +227,7 @@ static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x0, 0x0, 0x0}; static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; static const regdma_entries_config_t gdma_g0p4_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ G0P4_RETENTION_REGS_CNT_0, 0, 0, \ g0p4_regs_map0[0], g0p4_regs_map0[1], \ @@ -235,7 +235,7 @@ static const regdma_entries_config_t gdma_g0p4_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ G0P4_RETENTION_REGS_CNT_1, 0, 0, \ g0p4_regs_map1[0], g0p4_regs_map1[1], \ diff --git a/components/esp_driver_dma/esp32s31/gdma_retention.c b/components/esp_driver_dma/esp32s31/gdma_retention.c index 86dc49c3358..2448312a9f1 100644 --- a/components/esp_driver_dma/esp32s31/gdma_retention.c +++ b/components/esp_driver_dma/esp32s31/gdma_retention.c @@ -31,7 +31,7 @@ static const uint32_t g0p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x7 static const uint32_t g0p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \ G0P0_RETENTION_REGS_CNT_0, 0, 0, \ g0p0_regs_map0[0], g0p0_regs_map0[1], \ @@ -39,7 +39,7 @@ static const regdma_entries_config_t ahb_dma_g0p0_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \ G0P0_RETENTION_REGS_CNT_1, 0, 0, \ g0p0_regs_map1[0], g0p0_regs_map1[1], \ @@ -76,7 +76,7 @@ static const uint32_t g0p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; static const uint32_t g0p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \ G0P1_RETENTION_REGS_CNT_0, 0, 0, \ g0p1_regs_map0[0], g0p1_regs_map0[1], \ @@ -84,7 +84,7 @@ static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \ G0P1_RETENTION_REGS_CNT_1, 0, 0, \ g0p1_regs_map1[0], g0p1_regs_map1[1], \ @@ -92,7 +92,7 @@ static const regdma_entries_config_t ahb_dma_g0p1_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x02), \ G0P1_RETENTION_MAP_BASE_2, G0P1_RETENTION_MAP_BASE_2, \ G0P1_RETENTION_REGS_CNT_2, 0, 0, \ g0p1_regs_map2[0], g0p1_regs_map2[1], \ @@ -128,7 +128,7 @@ static const uint32_t g0p2_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; static const uint32_t g0p2_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \ G0P2_RETENTION_REGS_CNT_0, 0, 0, \ g0p2_regs_map0[0], g0p2_regs_map0[1], \ @@ -136,7 +136,7 @@ static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \ G0P2_RETENTION_REGS_CNT_1, 0, 0, \ g0p2_regs_map1[0], g0p2_regs_map1[1], \ @@ -144,7 +144,7 @@ static const regdma_entries_config_t ahb_dma_g0p2_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x02), \ G0P2_RETENTION_MAP_BASE_2, G0P2_RETENTION_MAP_BASE_2, \ G0P2_RETENTION_REGS_CNT_2, 0, 0, \ g0p2_regs_map2[0], g0p2_regs_map2[1], \ @@ -180,7 +180,7 @@ static const uint32_t g0p3_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; static const uint32_t g0p3_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; static const regdma_entries_config_t ahb_dma_g0p3_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P3_RETENTION_MAP_BASE_0, G0P3_RETENTION_MAP_BASE_0, \ G0P3_RETENTION_REGS_CNT_0, 0, 0, \ g0p3_regs_map0[0], g0p3_regs_map0[1], \ @@ -188,7 +188,7 @@ static const regdma_entries_config_t ahb_dma_g0p3_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P3_RETENTION_MAP_BASE_1, G0P3_RETENTION_MAP_BASE_1, \ G0P3_RETENTION_REGS_CNT_1, 0, 0, \ g0p3_regs_map1[0], g0p3_regs_map1[1], \ @@ -196,7 +196,7 @@ static const regdma_entries_config_t ahb_dma_g0p3_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [2] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x02), \ G0P3_RETENTION_MAP_BASE_2, G0P3_RETENTION_MAP_BASE_2, \ G0P3_RETENTION_REGS_CNT_2, 0, 0, \ g0p3_regs_map2[0], g0p3_regs_map2[1], \ @@ -228,7 +228,7 @@ static const uint32_t g0p4_regs_map0[4] = {0x900001, 0x0, 0x0, 0x0}; static const uint32_t g0p4_regs_map1[4] = {0x1e033, 0x1e033, 0x17, 0x0}; static const regdma_entries_config_t ahb_dma_g0p4_regs_retention[] = { [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ G0P4_RETENTION_MAP_BASE_0, G0P4_RETENTION_MAP_BASE_0, \ G0P4_RETENTION_REGS_CNT_0, 0, 0, \ g0p4_regs_map0[0], g0p4_regs_map0[1], \ @@ -236,7 +236,7 @@ static const regdma_entries_config_t ahb_dma_g0p4_regs_retention[] = { .owner = GDMA_RETENTION_ENTRY }, \ [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \ + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ G0P4_RETENTION_MAP_BASE_1, G0P4_RETENTION_MAP_BASE_1, \ G0P4_RETENTION_REGS_CNT_1, 0, 0, \ g0p4_regs_map1[0], g0p4_regs_map1[1], \ @@ -347,6 +347,99 @@ static const regdma_entries_config_t axi_dma_g1p2_regs_retention[] = { }, }; +/* LP_AHB_DMA (Group2, Pair0) Registers Context + Include: LP_AHB_DMA_MISC_CONF_REG + LP_AHB_DMA_IN_INT_ENA_CH0_REG / LP_AHB_DMA_OUT_INT_ENA_CH0_REG + LP_AHB_DMA_IN_CONF0_CH0_REG / LP_AHB_DMA_IN_CONF1_CH0_REG + LP_AHB_DMA_IN_LINK_CH0_REG / LP_AHB_DMA_IN_LINK_ADDR_CH0_REG + LP_AHB_DMA_IN_PRI_CH0_REG / LP_AHB_DMA_IN_PERI_SEL_CH0_REG + LP_AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / LP_AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + LP_AHB_DMA_OUT_CONF0_CH0_REG / LP_AHB_DMA_OUT_CONF1_CH0_REG + LP_AHB_DMA_OUT_LINK_CH0_REG / LP_AHB_DMA_OUT_LINK_ADDR_CH0_REG + LP_AHB_DMA_OUT_PRI_CH0_REG / LP_AHB_DMA_OUT_PERI_SEL_CH0_REG + LP_AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / LP_AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG + + LP_AHB_DMA_INTR_MEM_START_ADDR_REG / LP_AHB_DMA_INTR_MEM_END_ADDR_REG + LP_AHB_DMA_ARB_TIMEOUT_REG / LP_AHB_DMA_WEIGHT_EN_REG +*/ +#define LP_AHB_DMA_G2P0_RETENTION_REGS_CNT_0 19 +#define LP_AHB_DMA_G2P0_RETENTION_MAP_BASE_0 (DR_REG_LP_AHB_PDMA_BASE + 0x8) +#define LP_AHB_DMA_G2P0_RETENTION_REGS_CNT_1 4 +#define LP_AHB_DMA_G2P0_RETENTION_MAP_BASE_1 (DR_REG_LP_AHB_PDMA_BASE + 0x600) +static const uint32_t lp_ahb_dma_g2p0_regs_map0[4] = {0x100001, 0xc0000080, 0xc000780c, 0x780c}; +static const uint32_t lp_ahb_dma_g2p0_regs_map1[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t lp_ahb_dma_g2p0_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + LP_AHB_DMA_G2P0_RETENTION_MAP_BASE_0, LP_AHB_DMA_G2P0_RETENTION_MAP_BASE_0, \ + LP_AHB_DMA_G2P0_RETENTION_REGS_CNT_0, 0, 0, \ + lp_ahb_dma_g2p0_regs_map0[0], lp_ahb_dma_g2p0_regs_map0[1], \ + lp_ahb_dma_g2p0_regs_map0[2], lp_ahb_dma_g2p0_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + LP_AHB_DMA_G2P0_RETENTION_MAP_BASE_1, LP_AHB_DMA_G2P0_RETENTION_MAP_BASE_1, \ + LP_AHB_DMA_G2P0_RETENTION_REGS_CNT_1, 0, 0, \ + lp_ahb_dma_g2p0_regs_map1[0], lp_ahb_dma_g2p0_regs_map1[1], \ + lp_ahb_dma_g2p0_regs_map1[2], lp_ahb_dma_g2p0_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + +/* LP_AHB_DMA (Group2, Pair1) Registers Context + Include: LP_AHB_DMA_MISC_CONF_REG + LP_AHB_DMA_IN_INT_ENA_CH1_REG / LP_AHB_DMA_OUT_INT_ENA_CH1_REG + + LP_AHB_DMA_IN_CONF0_CH1_REG / LP_AHB_DMA_IN_CONF1_CH1_REG + LP_AHB_DMA_IN_LINK_CH1_REG / LP_AHB_DMA_IN_LINK_ADDR_CH1_REG + LP_AHB_DMA_IN_PRI_CH1_REG / LP_AHB_DMA_IN_PERI_SEL_CH1_REG + LP_AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / LP_AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + LP_AHB_DMA_OUT_CONF0_CH1_REG / LP_AHB_DMA_OUT_CONF1_CH1_REG + LP_AHB_DMA_OUT_LINK_CH1_REG / LP_AHB_DMA_OUT_LINK_ADDR_CH1_REG + LP_AHB_DMA_OUT_PRI_CH1_REG / LP_AHB_DMA_OUT_PERI_SEL_CH1_REG + LP_AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / LP_AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG + + LP_AHB_DMA_INTR_MEM_START_ADDR_REG / LP_AHB_DMA_INTR_MEM_END_ADDR_REG + LP_AHB_DMA_ARB_TIMEOUT_REG / LP_AHB_DMA_WEIGHT_EN_REG +*/ + +#define LP_AHB_DMA_G2P1_RETENTION_REGS_CNT_0 3 +#define LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_0 (DR_REG_LP_AHB_PDMA_BASE + 0x18) +#define LP_AHB_DMA_G2P1_RETENTION_REGS_CNT_1 16 +#define LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_1 (DR_REG_LP_AHB_PDMA_BASE + 0x200) +#define LP_AHB_DMA_G2P1_RETENTION_REGS_CNT_2 4 +#define LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_2 (DR_REG_LP_AHB_PDMA_BASE + 0x600) +static const uint32_t lp_ahb_dma_g2p1_regs_map0[4] = {0x100001, 0x8, 0x0, 0x0}; +static const uint32_t lp_ahb_dma_g2p1_regs_map1[4] = {0x1e033, 0x1e033, 0x0, 0x0}; +static const uint32_t lp_ahb_dma_g2p1_regs_map2[4] = {0x17, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t lp_ahb_dma_g2p1_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \ + LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_0, LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_0, \ + LP_AHB_DMA_G2P1_RETENTION_REGS_CNT_0, 0, 0, \ + lp_ahb_dma_g2p1_regs_map0[0], lp_ahb_dma_g2p1_regs_map0[1], \ + lp_ahb_dma_g2p1_regs_map0[2], lp_ahb_dma_g2p1_regs_map0[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [1] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x01), \ + LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_1, LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_1, \ + LP_AHB_DMA_G2P1_RETENTION_REGS_CNT_1, 0, 0, \ + lp_ahb_dma_g2p1_regs_map1[0], lp_ahb_dma_g2p1_regs_map1[1], \ + lp_ahb_dma_g2p1_regs_map1[2], lp_ahb_dma_g2p1_regs_map1[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x02), \ + LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_2, LP_AHB_DMA_G2P1_RETENTION_MAP_BASE_2, \ + LP_AHB_DMA_G2P1_RETENTION_REGS_CNT_2, 0, 0, \ + lp_ahb_dma_g2p1_regs_map2[0], lp_ahb_dma_g2p1_regs_map2[1], \ + lp_ahb_dma_g2p1_regs_map2[2], lp_ahb_dma_g2p1_regs_map2[3]), \ + .owner = GDMA_RETENTION_ENTRY + }, \ +}; + const gdma_retention_desc_t gdma_retention_infos[3][5] = { [0] = { [0] = { @@ -391,6 +484,17 @@ const gdma_retention_desc_t gdma_retention_infos[3][5] = { ARRAY_SIZE(axi_dma_g1p2_regs_retention), SLEEP_RETENTION_MODULE_AXI_DMA_CH2, }, - } - // LP_AHB_DMA (Group2) has no retention configuration because LP_AHB_DMA won't be powered off during light sleep + }, + [2] = { + [0] = { + lp_ahb_dma_g2p0_regs_retention, + ARRAY_SIZE(lp_ahb_dma_g2p0_regs_retention), + SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0, + }, + [1] = { + lp_ahb_dma_g2p1_regs_retention, + ARRAY_SIZE(lp_ahb_dma_g2p1_regs_retention), + SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1, + }, + }, }; diff --git a/components/esp_driver_dma/src/gdma.c b/components/esp_driver_dma/src/gdma.c index b4d5be044ca..b248ba2bad0 100644 --- a/components/esp_driver_dma/src/gdma.c +++ b/components/esp_driver_dma/src/gdma.c @@ -28,7 +28,6 @@ #include "gdma_priv.h" #include "esp_memory_utils.h" -#include "esp_sleep.h" #define GDMA_INVALID_PERIPH_TRIG (0x3F) #define SEARCH_REQUEST_RX_CHANNEL (1 << 0) @@ -88,15 +87,11 @@ static esp_err_t do_allocate_gdma_channel(const gdma_channel_search_info_t *sear TAG, "invalid interrupt priority:%d", config->intr_priority); } -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION // retention module is per GDMA pair, before we allocate the pair object, some common registers are already configured in "hal_init" // if a light sleep happens and powers off the gdma module, those registers will get lost // to work around it, we can acquire a power lock first, before any register configuration sleep_retention_power_lock_acquire(); -#else - esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_ON); //IDF-15640 -#endif #endif // Determine search code based on which channels are requested @@ -242,12 +237,8 @@ err: free(alloc_rx_channel); } -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION sleep_retention_power_lock_release(); -#else - esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_AUTO); //IDF-15640 -#endif #endif return ret; } @@ -883,13 +874,9 @@ static esp_err_t gdma_del_tx_channel(gdma_channel_t *dma_channel) free(tx_chan); ESP_LOGV(TAG, "del tx channel (%d,%d)", group_id, pair_id); -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION // release sleep retention lock gdma_release_sleep_retention(pair); -#else - esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_AUTO); //IDF-15640 -#endif #endif // release pair handle (will free pair if both channels are deleted) gdma_try_free_pair_handle(pair); @@ -922,13 +909,9 @@ static esp_err_t gdma_del_rx_channel(gdma_channel_t *dma_channel) free(rx_chan); ESP_LOGV(TAG, "del rx channel (%d,%d)", group_id, pair_id); -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP -#if SOC_GDMA_SUPPORT_SLEEP_RETENTION +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_GDMA_SUPPORT_SLEEP_RETENTION // release sleep retention lock gdma_release_sleep_retention(pair); -#else - esp_sleep_pd_config(ESP_PD_DOMAIN_TOP, ESP_PD_OPTION_AUTO); //IDF-15640 -#endif #endif // release pair handle (will free pair if both channels are deleted) gdma_try_free_pair_handle(pair); diff --git a/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c b/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c index 142a71bc37c..4fdbde18c3d 100644 --- a/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c +++ b/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c @@ -40,6 +40,10 @@ bool peripheral_domain_pd_allowed(void) RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH1); RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH2); + // ESP32S31 supports LP_AHB_DMA sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1); + // ESP32S31 supports UART sleep retention RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART0); RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART1); diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 6d51a868552..12f2fab4b06 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -435,6 +435,10 @@ config SOC_GDMA_SUPPORT_ETM bool default y +config SOC_GDMA_SUPPORT_SLEEP_RETENTION + bool + default y + config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT int default 16 diff --git a/components/soc/esp32s31/include/soc/retention_periph_defs.h b/components/soc/esp32s31/include/soc/retention_periph_defs.h index 571f97a4c15..7efc815762b 100644 --- a/components/soc/esp32s31/include/soc/retention_periph_defs.h +++ b/components/soc/esp32s31/include/soc/retention_periph_defs.h @@ -39,40 +39,43 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 15, SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 16, SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 17, + /* LP_AHB_DMA by channel */ + SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH0 = 18, + SLEEP_RETENTION_MODULE_LP_AHB_DMA_CH1 = 19, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_UART0 = 18, - SLEEP_RETENTION_MODULE_UART1 = 19, - SLEEP_RETENTION_MODULE_UART2 = 20, - SLEEP_RETENTION_MODULE_UART3 = 21, - SLEEP_RETENTION_MODULE_RMT0 = 22, - SLEEP_RETENTION_MODULE_I2S0 = 23, - SLEEP_RETENTION_MODULE_I2S1 = 24, - SLEEP_RETENTION_MODULE_I2C0 = 25, - SLEEP_RETENTION_MODULE_I2C1 = 26, - SLEEP_RETENTION_MODULE_ETM0 = 27, - SLEEP_RETENTION_MODULE_TWAI0 = 28, - SLEEP_RETENTION_MODULE_TWAI1 = 29, - SLEEP_RETENTION_MODULE_PARLIO0 = 30, - SLEEP_RETENTION_MODULE_GPSPI2 = 31, - SLEEP_RETENTION_MODULE_GPSPI3 = 32, - SLEEP_RETENTION_MODULE_LEDC0 = 33, - SLEEP_RETENTION_MODULE_LEDC1 = 34, - SLEEP_RETENTION_MODULE_MCPWM0 = 35, - SLEEP_RETENTION_MODULE_MCPWM1 = 36, - SLEEP_RETENTION_MODULE_MCPWM2 = 37, - SLEEP_RETENTION_MODULE_MCPWM3 = 38, - SLEEP_RETENTION_MODULE_SDM0 = 39, - SLEEP_RETENTION_MODULE_LCDCAM = 40, - SLEEP_RETENTION_MODULE_JPEG = 41, + SLEEP_RETENTION_MODULE_UART0 = 20, + SLEEP_RETENTION_MODULE_UART1 = 21, + SLEEP_RETENTION_MODULE_UART2 = 22, + SLEEP_RETENTION_MODULE_UART3 = 23, + SLEEP_RETENTION_MODULE_RMT0 = 24, + SLEEP_RETENTION_MODULE_I2S0 = 25, + SLEEP_RETENTION_MODULE_I2S1 = 26, + SLEEP_RETENTION_MODULE_I2C0 = 27, + SLEEP_RETENTION_MODULE_I2C1 = 28, + SLEEP_RETENTION_MODULE_ETM0 = 29, + SLEEP_RETENTION_MODULE_TWAI0 = 30, + SLEEP_RETENTION_MODULE_TWAI1 = 31, + SLEEP_RETENTION_MODULE_PARLIO0 = 32, + SLEEP_RETENTION_MODULE_GPSPI2 = 33, + SLEEP_RETENTION_MODULE_GPSPI3 = 34, + SLEEP_RETENTION_MODULE_LEDC0 = 35, + SLEEP_RETENTION_MODULE_LEDC1 = 36, + SLEEP_RETENTION_MODULE_MCPWM0 = 37, + SLEEP_RETENTION_MODULE_MCPWM1 = 38, + SLEEP_RETENTION_MODULE_MCPWM2 = 39, + SLEEP_RETENTION_MODULE_MCPWM3 = 40, + SLEEP_RETENTION_MODULE_SDM0 = 41, + SLEEP_RETENTION_MODULE_LCDCAM = 42, + SLEEP_RETENTION_MODULE_JPEG = 43, /* Modem module, which includes WiFi, BLE and 802.15.4 */ - SLEEP_RETENTION_MODULE_WIFI_MAC = 43, - SLEEP_RETENTION_MODULE_WIFI_BB = 44, - SLEEP_RETENTION_MODULE_BLE_MAC = 45, - SLEEP_RETENTION_MODULE_BT_BB = 46, - SLEEP_RETENTION_MODULE_802154_MAC = 47, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 48, - SLEEP_RETENTION_MODULE_MODEM_PHY = 49, + SLEEP_RETENTION_MODULE_WIFI_MAC = 44, + SLEEP_RETENTION_MODULE_WIFI_BB = 45, + SLEEP_RETENTION_MODULE_BLE_MAC = 46, + SLEEP_RETENTION_MODULE_BT_BB = 47, + SLEEP_RETENTION_MODULE_802154_MAC = 48, + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 49, + SLEEP_RETENTION_MODULE_MODEM_PHY = 50, SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index d9eb204314c..ec702dc9783 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -169,7 +169,7 @@ /*-------------------------- GDMA CAPS -------------------------------------*/ #define SOC_AHB_GDMA_VERSION 2 #define SOC_GDMA_SUPPORT_ETM 1 -// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32S31] IDF-14760 +#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 #define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT (16) /*-------------------------- APM CAPS ----------------------------------------*/ diff --git a/components/soc/include/soc/regdma.h b/components/soc/include/soc/regdma.h index f7e8e680c4b..471959ca104 100644 --- a/components/soc/include/soc/regdma.h +++ b/components/soc/include/soc/regdma.h @@ -49,7 +49,6 @@ extern "C" { #define REGDMA_MODEM_BT_BB_LINK(_pri) ((0x15 << 8) | _pri) #define REGDMA_MODEM_IEEE802154_LINK(_pri) ((0x16 << 8) | _pri) #define REGDMA_GDMA_LINK(_pri) ((0x17 << 8) | _pri) -#define REGDMA_AHB_DMA_LINK(_pri) ((0x17 << 8) | _pri) #define REGDMA_I2C_LINK(_pri) ((0x18 << 8) | _pri) #define REGDMA_RMT_LINK(_pri) ((0x19 << 8) | _pri) #define REGDMA_TG0_WDT_LINK(_pri) ((0x1A << 8) | _pri)