Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(esp_hw_support): do esp32p4 l1&l2 cache regs retention by regdma

Browse Source
This commit is contained in:
wuzhenghui
2025-02-19 21:32:15 +08:00
parent 1698a58881
commit ca9cca73ff
7 changed files with 50 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu.c
+1 -27
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,7 +20,6 @@
#include "freertos/task.h"
#include "esp_heap_caps.h"
#include "riscv/csr.h"
#include "soc/cache_reg.h"
#include "soc/clic_reg.h"
#include "soc/rtc_periph.h"
#include "soc/soc_caps.h"
@@ -32,7 +31,6 @@
#include "esp32p4/rom/ets_sys.h"
#include "esp32p4/rom/rtc.h"
#include "esp32p4/rom/cache.h"
#include "rvsleep-frames.h"
#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
@@ -76,7 +74,6 @@ typedef struct {
struct {
RvCoreCriticalSleepFrame *critical_frame[portNUM_PROCESSORS];
RvCoreNonCriticalSleepFrame *non_critical_frame[portNUM_PROCESSORS];
cpu_domain_dev_sleep_frame_t *cache_config_frame;
cpu_domain_dev_sleep_frame_t *clic_frame[portNUM_PROCESSORS];
} retent;
} sleep_cpu_retention_t;
@@ -107,15 +104,6 @@ static void * cpu_domain_dev_sleep_frame_alloc_and_init(const cpu_domain_dev_reg
return frame;
}
static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void)
{
const static cpu_domain_dev_regs_region_t regions[] = {
{ .start = CACHE_L1_ICACHE_CTRL_REG, .end = CACHE_L1_BYPASS_CACHE_CONF_REG + 4 },
{ .start = CACHE_L2_CACHE_CTRL_REG, .end = CACHE_L2_CACHE_BLOCKSIZE_CONF_REG + 4 }
};
return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
}
static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(uint8_t core_id)
{
const static cpu_domain_dev_regs_region_t regions[portNUM_PROCESSORS][2] = {
@@ -146,13 +134,6 @@ static esp_err_t esp_sleep_cpu_retention_init_impl(void)
s_cpu_retention.retent.non_critical_frame[core_id] = (RvCoreNonCriticalSleepFrame *)frame;
}
}
if (s_cpu_retention.retent.cache_config_frame == NULL) {
void *frame = cpu_domain_cache_config_sleep_frame_alloc_and_init();
if (frame == NULL) {
goto err;
}
s_cpu_retention.retent.cache_config_frame = (cpu_domain_dev_sleep_frame_t *)frame;
}
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
if (s_cpu_retention.retent.clic_frame[core_id] == NULL) {
void *frame = cpu_domain_clic_sleep_frame_alloc_and_init(core_id);
@@ -186,10 +167,6 @@ static esp_err_t esp_sleep_cpu_retention_deinit_impl(void)
s_cpu_retention.retent.non_critical_frame[core_id] = NULL;
}
}
if (s_cpu_retention.retent.cache_config_frame) {
heap_caps_free((void *)s_cpu_retention.retent.cache_config_frame);
s_cpu_retention.retent.cache_config_frame = NULL;
}
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
if (s_cpu_retention.retent.clic_frame[core_id]) {
heap_caps_free((void *)s_cpu_retention.retent.clic_frame[core_id]);
@@ -442,7 +419,6 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START);
#endif
cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame[core_id]);
cpu_domain_dev_regs_save(s_cpu_retention.retent.cache_config_frame);
rv_core_noncritical_regs_save();
#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
@@ -468,7 +444,6 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
#endif
rv_core_noncritical_regs_restore();
cpu_domain_dev_regs_restore(s_cpu_retention.retent.cache_config_frame);
cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame[core_id]);
restore_mstatus(mstatus);
@@ -495,7 +470,6 @@ bool cpu_domain_pd_allowed(void)
allowed &= (s_cpu_retention.retent.critical_frame[core_id] != NULL);
allowed &= (s_cpu_retention.retent.non_critical_frame[core_id] != NULL);
}
allowed &= (s_cpu_retention.retent.cache_config_frame != NULL);
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
allowed &= (s_cpu_retention.retent.clic_frame[core_id] != NULL);
}
components/esp_hw_support/sleep_system_peripheral.c
+7 -7
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -99,11 +99,11 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_systimer_retention_ini
return ESP_OK;
}
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
esp_err_t sleep_sys_periph_l2_cache_retention_init(void)
#if SOC_PM_CACHE_RETENTION_BY_PAU
esp_err_t sleep_sys_periph_cache_retention_init(void)
{
esp_err_t err = sleep_retention_entries_create(l2_cache_regs_retention, ARRAY_SIZE(l2_cache_regs_retention), REGDMA_LINK_PRI_SYS_PERIPH_HIGH, SLEEP_RETENTION_MODULE_SYS_PERIPH);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (L2 Cache) retention");
esp_err_t err = sleep_retention_entries_create(cache_regs_retention, ARRAY_SIZE(cache_regs_retention), REGDMA_LINK_PRI_SYS_PERIPH_HIGH, SLEEP_RETENTION_MODULE_SYS_PERIPH);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (Cache) retention");
ESP_LOGI(TAG, "L2 Cache sleep retention initialization");
return ESP_OK;
}
@@ -126,8 +126,8 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
if(err) goto error;
err = sleep_sys_periph_hp_system_retention_init(arg);
if(err) goto error;
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
err = sleep_sys_periph_l2_cache_retention_init();
#if SOC_PM_CACHE_RETENTION_BY_PAU
err = sleep_sys_periph_cache_retention_init();
if(err) goto error;
#endif
#if SOC_APM_SUPPORTED