feat(gpio): support fast gpio driver on esp32h4

components/esp_driver_gpio/test_apps/gpio_extensions/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |

components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c

@@ -136,6 +136,8 @@ TEST_CASE("Dedicated_GPIO_run_on_multiple_CPU_cores", "[dedic_gpio]")
     for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
 #if CONFIG_IDF_TARGET_ESP32P4
         int start_gpio = i * TEST_GPIO_GROUP_SIZE + 20;
+#elif CONFIG_IDF_TARGET_ESP32H4
+        int start_gpio = i * TEST_GPIO_GROUP_SIZE + 13;
 #else
         int start_gpio = i * TEST_GPIO_GROUP_SIZE;
 #endif

components/hal/esp32h4/include/hal/dedic_gpio_cpu_ll.h

@@ -0,0 +1,58 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "riscv/csr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*fast gpio*/
+#define CSR_GPIO_OEN_USER   0x803
+#define CSR_GPIO_IN_USER    0x804
+#define CSR_GPIO_OUT_USER   0x805
+
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
+
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
+{
+    RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
+}
+
+static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
+{
+    RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
+}
+
+__attribute__((always_inline))
+static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
+{
+    uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
+    return value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
+{
+    uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
+    return value;
+}
+
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
+{
+    RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
+    RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value));
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h4/include/hal/gpio_glitch_filter_ll.h

@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "soc/gpio_ext_struct.h"
+
+#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW  64
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable GPIO glitch filter
+ *
+ * @param hw Glitch filter register base address
+ * @param filter_idx Glitch filter index
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_glitch_filter_enable(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, bool enable)
+{
+    hw->glitch_filter_chn[filter_idx].ext_filter_chn_en = enable;
+}
+
+/**
+ * @brief Set the input GPIO for the glitch filter
+ *
+ * @param hw Glitch filter register base address
+ * @param filter_idx Glitch filter index
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_glitch_filter_set_gpio(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t gpio_num)
+{
+    hw->glitch_filter_chn[filter_idx].ext_filter_chn_input_io_num = gpio_num;
+}
+
+/**
+ * @brief Set the coefficient of the glitch filter window
+ *
+ * @param hw Glitch filter register base address
+ * @param filter_idx Glitch filter index
+ * @param window_width Window width, in IOMUX clock ticks
+ * @param window_threshold Window threshold, in IOMUX clock ticks
+ */
+static inline void gpio_ll_glitch_filter_set_window_coeff(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t window_width, uint32_t window_thres)
+{
+    HAL_ASSERT(window_thres <= window_width);
+    hw->glitch_filter_chn[filter_idx].ext_filter_chn_window_width = window_width - 1;
+    hw->glitch_filter_chn[filter_idx].ext_filter_chn_window_thres = window_thres - 1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h4/dedic_gpio_periph.c

@@ -0,0 +1,58 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gpio_sig_map.h"
+#include "soc/dedic_gpio_periph.h"
+
+const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
+    .irq = -1,
+    .cores = {
+        [0] = {
+            .in_sig_per_channel = {
+                [0] = CPU0_GPIO_IN0_IDX,
+                [1] = CPU0_GPIO_IN1_IDX,
+                [2] = CPU0_GPIO_IN2_IDX,
+                [3] = CPU0_GPIO_IN3_IDX,
+                [4] = CPU0_GPIO_IN4_IDX,
+                [5] = CPU0_GPIO_IN5_IDX,
+                [6] = CPU0_GPIO_IN6_IDX,
+                [7] = CPU0_GPIO_IN7_IDX,
+            },
+            .out_sig_per_channel = {
+                [0] = CPU0_GPIO_OUT0_IDX,
+                [1] = CPU0_GPIO_OUT1_IDX,
+                [2] = CPU0_GPIO_OUT2_IDX,
+                [3] = CPU0_GPIO_OUT3_IDX,
+                [4] = CPU0_GPIO_OUT4_IDX,
+                [5] = CPU0_GPIO_OUT5_IDX,
+                [6] = CPU0_GPIO_OUT6_IDX,
+                [7] = CPU0_GPIO_OUT7_IDX,
+            }
+        },
+        [1] = {
+            .in_sig_per_channel = {
+                [0] = CPU1_GPIO_IN0_IDX,
+                [1] = CPU1_GPIO_IN1_IDX,
+                [2] = CPU1_GPIO_IN2_IDX,
+                [3] = CPU1_GPIO_IN3_IDX,
+                [4] = CPU1_GPIO_IN4_IDX,
+                [5] = CPU1_GPIO_IN5_IDX,
+                [6] = CPU1_GPIO_IN6_IDX,
+                [7] = CPU1_GPIO_IN7_IDX,
+            },
+            .out_sig_per_channel = {
+                [0] = CPU1_GPIO_OUT0_IDX,
+                [1] = CPU1_GPIO_OUT1_IDX,
+                [2] = CPU1_GPIO_OUT2_IDX,
+                [3] = CPU1_GPIO_OUT3_IDX,
+                [4] = CPU1_GPIO_OUT4_IDX,
+                [5] = CPU1_GPIO_OUT5_IDX,
+                [6] = CPU1_GPIO_OUT6_IDX,
+                [7] = CPU1_GPIO_OUT7_IDX,
+            }
+        },
+    },
+};

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -3,6 +3,10 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
+config SOC_DEDICATED_GPIO_SUPPORTED
+    bool
+    default y
+
 config SOC_UART_SUPPORTED
     bool
     default y
@@ -291,6 +295,14 @@ config SOC_GPIO_OUT_RANGE_MAX
     int
     default 39
 
+config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
+    bool
+    default y
+
+config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
+    int
+    default 8
+
 config SOC_GPIO_SUPPORT_ETM
     bool
     default y

components/soc/esp32h4/include/soc/clk_tree_defs.h

@@ -428,6 +428,23 @@ typedef enum {
     SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,  /*!< Select PLL_F48M clock as the default clock choice */
 } soc_periph_sdm_clk_src_t;
 
+//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Glitch Filter
+ */
+#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Glitch filter clock source
+ */
+
+typedef enum {
+    GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,  /*!< Select PLL_F48M clock as the default clock choice */
+} soc_periph_glitch_filter_clk_src_t;
+
 //////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32h4/include/soc/soc_caps.h

@@ -33,7 +33,7 @@
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1    // TODO: [ESP32H4] IDF-12368 IDF-12370
 // #define SOC_ANA_CMPR_SUPPORTED          1    // TODO: [ESP32H4] IDF-12395 big change!!
-// #define SOC_DEDICATED_GPIO_SUPPORTED    1    // TODO: [ESP32H4] IDF-12401
+#define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_UART_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
 #define SOC_AHB_GDMA_SUPPORTED          1
@@ -201,8 +201,8 @@
 #define SOC_GPIO_VALID_GPIO_MASK            ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK     SOC_GPIO_VALID_GPIO_MASK
 
-// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1  // TODO: [ESP32H4] IDF-12391
+#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
-// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8  // TODO: [ESP32H4] IDF-12391
+#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
 
 // GPIO peripheral has the ETM extension
 #define SOC_GPIO_SUPPORT_ETM          1

components/soc/esp32h4/include/soc/soc_caps_full.h

@@ -9,6 +9,10 @@
 #include "soc/soc_caps.h"
 #include "soc/soc_caps_eval.h"
 
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */
+
 /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
 #define _SOC_CAPS_SDM_INST_NUM                    1  // Number of SDM instances
 #define _SOC_CAPS_SDM_CHANS_PER_INST              4  // Number of channels in each SDM instance

components/soc/esp32h4/register/soc/gpio_ext_struct.h

@@ -53,13 +53,13 @@ typedef union {
  */
 typedef union {
     struct {
-        /** ext_filter_ch0_en : R/W; bitpos: [0]; default: 0;
+        /** ext_filter_chn_en : R/W; bitpos: [0]; default: 0;
          *  Configures whether or not to enable channel n of Glitch Filter.
          *  0: Not enable
          *  1: Enable
          */
-        uint32_t ext_filter_ch0_en:1;
+        uint32_t ext_filter_chn_en:1;
-        /** ext_filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
+        /** ext_filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
          *  Configures to select the input GPIO for Glitch Filter.
          *  0: Select GPIO0
          *  1: Select GPIO1
@@ -68,21 +68,21 @@ typedef union {
          *  39: Select GPIO39
          *  40 ~ 63: Reserved
          */
-        uint32_t ext_filter_ch0_input_io_num:6;
+        uint32_t ext_filter_chn_input_io_num:6;
         uint32_t reserved_7:1;
-        /** ext_filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0;
+        /** ext_filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0;
          *  Configures the window threshold for Glitch Filter. The window threshold should be
          *  less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.
          *  %see DOC-4768
          *  Measurement unit: IO MUX operating clock cycle
          */
-        uint32_t ext_filter_ch0_window_thres:6;
+        uint32_t ext_filter_chn_window_thres:6;
-        /** ext_filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0;
+        /** ext_filter_chn_window_width : R/W; bitpos: [19:14]; default: 0;
          *  Configures the window width for Glitch Filter. The effective value of window width
          *  is 0 ~ 63.
          *  Measurement unit: IO MUX operating clock cycle
          */
-        uint32_t ext_filter_ch0_window_width:6;
+        uint32_t ext_filter_chn_window_width:6;
         uint32_t reserved_20:12;
     };
     uint32_t val;

docs/docs_not_updated/esp32h4.txt

@@ -120,12 +120,8 @@ api-reference/bluetooth/esp_a2dp.rst
 api-reference/bluetooth/esp_hf_defs.rst
 api-reference/peripherals/cap_touch_sens.rst
 api-reference/peripherals/index.rst
-api-reference/peripherals/rmt.rst
-api-reference/peripherals/gptimer.rst
 api-reference/peripherals/sdio_slave.rst
-api-reference/peripherals/bitscrambler.rst
 api-reference/peripherals/temp_sensor.rst
-api-reference/peripherals/jpeg.rst
 api-reference/peripherals/camera_driver.rst
 api-reference/peripherals/adc_oneshot.rst
 api-reference/peripherals/sdspi_share.rst
@@ -135,35 +131,23 @@ api-reference/peripherals/hmac.rst
 api-reference/peripherals/sdspi_host.rst
 api-reference/peripherals/vad.rst
 api-reference/peripherals/i2s.rst
-api-reference/peripherals/isp.rst
-api-reference/peripherals/dedic_gpio.rst
 api-reference/peripherals/sd_pullup_requirements.rst
 api-reference/peripherals/parlio.rst
 api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/lp_i2s.rst
 api-reference/peripherals/ecdsa.rst
-api-reference/peripherals/dac.rst
 api-reference/peripherals/spi_flash/index.rst
 api-reference/peripherals/spi_flash/spi_flash_concurrency.rst
 api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
 api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst
 api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst
 api-reference/peripherals/sdmmc_host.rst
-api-reference/peripherals/lcd/i80_lcd.rst
-api-reference/peripherals/lcd/index.rst
-api-reference/peripherals/lcd/dsi_lcd.rst
-api-reference/peripherals/lcd/spi_lcd.rst
-api-reference/peripherals/lcd/rgb_lcd.rst
-api-reference/peripherals/lcd/parl_lcd.rst
-api-reference/peripherals/ppa.rst
-api-reference/peripherals/ldo_regulator.rst
 api-reference/system/random.rst
 api-reference/system/app_trace.rst
 api-reference/system/mm_sync.rst
 api-reference/system/mm.rst
 api-reference/system/esp_https_ota.rst
 api-reference/system/sleep_modes.rst
-api-reference/system/async_memcpy.rst
 api-reference/system/ota.rst
 api-reference/system/efuse.rst
 api-reference/system/inc/power_management_esp32h4.rst

docs/en/api-reference/peripherals/dedic_gpio.rst

@@ -146,7 +146,7 @@ Application Example
     * :example:`peripherals/dedicated_gpio/soft_i2c` demonstrates how to configure and use dedicated/fast GPIOs to emulate an I2C master, perform write-read transactions on the bus, and handle strict timing requirements by placing certain functions in IRAM.
     * :example:`peripherals/dedicated_gpio/soft_uart` demonstrates how to emulate a UART bus using dedicated/fast GPIOs on {IDF_TARGET_NAME}, which can send and receive characters on the UART bus using a TX pin and an RX pin, with the baud rate and other configurations adjustable via `menuconfig`.
 
-    .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 or esp32p4
+    .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
         * :example:`peripherals/dedicated_gpio/soft_spi` demonstrates how to configure and use dedicated/fast GPIOs to emulate a full-duplex SPI bus on {IDF_TARGET_NAME}.
 

docs/zh_CN/api-reference/peripherals/dedic_gpio.rst

@@ -146,7 +146,7 @@ GPIO 捆绑包操作
     * :example:`peripherals/dedicated_gpio/soft_i2c` 演示了如何配置和使用专用/快速 GPIO 来模拟 I2C 主机设备、执行总线上的读写操作、以及通过将某些函数放在 IRAM 中来满足严格的时序要求。
     * :example:`peripherals/dedicated_gpio/soft_uart` 演示了如何使用专用/快速 GPIO 在 {IDF_TARGET_NAME} 上模拟 UART 总线。可以通过 TX 管脚和 RX 管脚在 UART 总线上发送和接收字符，还可以通过 `menuconfig` 来调整波特率和其他配置。
 
-    .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2 or esp32p4
+    .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
         * :example:`peripherals/dedicated_gpio/soft_spi` 演示了如何配置和使用专用/快速 GPIO，在 {IDF_TARGET_NAME} 上模拟全双工 SPI 总线。
 

examples/peripherals/dedicated_gpio/soft_i2c/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
 
 # Example: Software I2C Master via Dedicated/Fast GPIOs
 

examples/peripherals/dedicated_gpio/soft_spi/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
 
 # Example: SPI software emulation using dedicated/fast GPIOs
 

examples/peripherals/dedicated_gpio/soft_uart/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
 
 # Example: UART software emulation using dedicated/fast GPIOs