diff --git a/components/esp_driver_dma/src/gdma.c b/components/esp_driver_dma/src/gdma.c
index 488c38bf887..b73d5a51257 100644
--- a/components/esp_driver_dma/src/gdma.c
+++ b/components/esp_driver_dma/src/gdma.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -416,6 +416,21 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
     // always enable descriptor burst as the descriptor is always word aligned and is in the internal SRAM
     bool en_desc_burst = true;
     bool en_data_burst = max_data_burst_size > 0;
+
+#if SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH
+    // if MSPI encryption is enabled, and DMA wants to read/write external memory
+    if (efuse_hal_flash_encryption_enabled() && config->access_ext_mem) {
+        uint32_t enc_mem_alignment = GDMA_LL_GET(ACCESS_ENCRYPTION_MEM_ALIGNMENT);
+        // when DMA access the encrypted external memory, extra alignment is needed for external memory
+        ext_mem_alignment = MAX(ext_mem_alignment, enc_mem_alignment);
+        if (max_data_burst_size < enc_mem_alignment) {
+            ESP_LOGW(TAG, "GDMA channel access encrypted external memory, adjust burst size to %d", enc_mem_alignment);
+            en_data_burst = true;
+            max_data_burst_size = enc_mem_alignment;
+        }
+    }
+#endif // SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH
+
     gdma_hal_enable_burst(hal, pair->pair_id, dma_chan->direction, en_data_burst, en_desc_burst);
     if (en_data_burst) {
         gdma_hal_set_burst_size(hal, pair->pair_id, dma_chan->direction, max_data_burst_size);
@@ -433,26 +448,6 @@ esp_err_t gdma_config_transfer(gdma_channel_handle_t dma_chan, const gdma_transf
     }
 #endif
 
-    // if MSPI encryption is enabled, and DMA wants to read/write external memory
-    if (efuse_hal_flash_encryption_enabled()) {
-        gdma_hal_enable_access_encrypt_mem(hal, pair->pair_id, dma_chan->direction, config->access_ext_mem);
-#if SOC_PSRAM_DMA_CAPABLE || SOC_DMA_CAN_ACCESS_FLASH
-        uint32_t enc_mem_alignment = GDMA_LL_GET(ACCESS_ENCRYPTION_MEM_ALIGNMENT);
-        // when DMA access the encrypted external memory, extra alignment is needed for external memory
-        if (config->access_ext_mem) {
-            ext_mem_alignment = MAX(ext_mem_alignment, enc_mem_alignment);
-        }
-#if SOC_HAS(AXI_GDMA)
-        if (group->bus_id == SOC_GDMA_BUS_AXI) {
-            // once AXI-GDMA enables access to encrypted memory, internal memory also needs to align
-            int_mem_alignment = MAX(int_mem_alignment, enc_mem_alignment);
-        }
-#endif // SOC_HAS(AXI_GDMA)
-#endif // SOC_PSRAM_DMA_CAPABLE
-    } else {
-        gdma_hal_enable_access_encrypt_mem(hal, pair->pair_id, dma_chan->direction, false);
-    }
-
     // if the channel is not allowed to access external memory, set a super big (meaningless) alignment value
     // so when the upper layer checks the alignment with an external buffer, the check should fail
     if (!config->access_ext_mem) {
diff --git a/components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h b/components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h
index 290047b1273..9b8b32d0416 100644
--- a/components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h
+++ b/components/esp_hal_dma/esp32p4/include/hal/axi_dma_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -302,6 +302,9 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
 
 /**
  * @brief Whether to enable access to ecc or aes memory
+ *
+ * @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
+ *       We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
  */
 static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
@@ -543,6 +546,9 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
 
 /**
  * @brief Whether to enable access to ecc or aes memory
+ *
+ * @note This function is not used for AXI-GDMA because it will affect the alignment requirement for internal memory.
+ *       We have ensured that the AXI-GDMA can access the encrypted memory by 16-bytes alignment in software.
  */
 static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
 {
diff --git a/components/esp_hal_dma/gdma_hal_axi.c b/components/esp_hal_dma/gdma_hal_axi.c
index f92af635858..c3a6b9ad116 100644
--- a/components/esp_hal_dma/gdma_hal_axi.c
+++ b/components/esp_hal_dma/gdma_hal_axi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -170,15 +170,6 @@ uint32_t gdma_axi_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gd
     }
 }
 
-void gdma_axi_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis)
-{
-    if (dir == GDMA_CHANNEL_DIRECTION_RX) {
-        axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(hal->axi_dma_dev, chan_id, en_or_dis);
-    } else {
-        axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(hal->axi_dma_dev, chan_id, en_or_dis);
-    }
-}
-
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_axi_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
 {
@@ -266,7 +257,6 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
     hal->get_intr_status_reg = gdma_axi_hal_get_intr_status_reg;
     hal->get_eof_desc_addr = gdma_axi_hal_get_eof_desc_addr;
     hal->set_burst_size = gdma_axi_hal_set_burst_size;
-    hal->enable_access_encrypt_mem = gdma_axi_hal_enable_access_encrypt_mem;
 #if SOC_GDMA_SUPPORT_CRC
     hal->clear_crc = gdma_axi_hal_clear_crc;
     hal->set_crc_poly = gdma_axi_hal_set_crc_poly;
diff --git a/components/esp_hal_dma/gdma_hal_top.c b/components/esp_hal_dma/gdma_hal_top.c
index 04e82977d2b..b1ebc075b26 100644
--- a/components/esp_hal_dma/gdma_hal_top.c
+++ b/components/esp_hal_dma/gdma_hal_top.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -95,13 +95,6 @@ uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_c
     return hal->get_eof_desc_addr(hal, chan_id, dir, is_success);
 }
 
-void gdma_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis)
-{
-    if (hal->enable_access_encrypt_mem) {
-        hal->enable_access_encrypt_mem(hal, chan_id, dir, en_or_dis);
-    }
-}
-
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
 {
diff --git a/components/esp_hal_dma/include/hal/gdma_hal.h b/components/esp_hal_dma/include/hal/gdma_hal.h
index 6d0eeecd47d..9c670c87d52 100644
--- a/components/esp_hal_dma/include/hal/gdma_hal.h
+++ b/components/esp_hal_dma/include/hal/gdma_hal.h
@@ -91,7 +91,6 @@ struct gdma_hal_context_t {
     void (*clear_intr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask); /// Clear the channel interrupt
     uint32_t (*read_intr_status)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw); /// Read the channel interrupt status
     uint32_t (*get_eof_desc_addr)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success); /// Get the address of the descriptor with success/error EOF flag set
-    void (*enable_access_encrypt_mem)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis); /// Enable the access to the encrypted memory
 #if SOC_GDMA_SUPPORT_CRC
     void (*clear_crc)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir); /// Clear the CRC interim results
     void (*set_crc_poly)(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config); /// Set the CRC polynomial
@@ -139,8 +138,6 @@ uint32_t gdma_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_ch
 
 uint32_t gdma_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success);
 
-void gdma_hal_enable_access_encrypt_mem(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis);
-
 #if SOC_GDMA_SUPPORT_CRC
 void gdma_hal_build_parallel_crc_matrix(int crc_width, uint32_t crc_poly_hex, int data_width,
                                         uint32_t *lfsr_transform_matrix, uint32_t *data_transform_matrix);