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feat(spi_flash): Add exclusive support for ESP32H4

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Add 32bit addr support for esp32s31 as well
This commit is contained in:
Song Ruo Jing
2026-06-09 15:27:41 +08:00
parent 519334d640
commit c9f52c7ca7
35 changed files with 647 additions and 356 deletions
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components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
-1
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@@ -69,7 +69,6 @@
#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
// Just use the same pins for HSPI
#define SPI2_PIN_NUM_MOSI 5
#define SPI2_PIN_NUM_MISO 0
#define SPI2_PIN_NUM_CLK 4
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
+1 -1
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@@ -600,7 +600,7 @@ TEST_CASE_MULTI_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_togg
#if CONFIG_IDF_TARGET_ESP32C2
uint8_t flash_frequency_table[4] = {5, 10, 20, 40};
#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
uint8_t flash_frequency_table[4] = {6, 12, 24, 48};
uint8_t flash_frequency_table[3] = {8, 16, 32}; // + 64
#else
uint8_t flash_frequency_table[6] = {5, 10, 20, 26, 40, 80};
#endif
components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c
+1 -1
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@@ -122,7 +122,7 @@ TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_fla
}
// TODO: This test is disabled on S3 with legacy impl - IDF-3505
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4, ESP32S31)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4, ESP32S31, ESP32H4)
#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
typedef struct {
components/spi_flash/test_apps/flash_suspend/main/test_flash_suspend.c
+4 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -75,14 +75,12 @@ static bool IRAM_ATTR gptimer_alarm_suspend_cb(gptimer_handle_t timer, const gpt
/*clear content in cache*/
#if CONFIG_IDF_TARGET_ESP32S3
Cache_Invalidate_DCache_All();
#endif
#if CONFIG_IDF_TARGET_ESP32P4
Cache_Invalidate_ICache_All();
#elif CONFIG_IDF_TARGET_ESP32P4
Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
#elif CONFIG_IDF_TARGET_ESP32H4
cache_ll_invalidate_all(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL);
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
Cache_Invalidate_All();
#elif CONFIG_IDF_TARGET_ESP32S31
#elif CONFIG_IDF_TARGET_ESP32S31 || CONFIG_IDF_TARGET_ESP32H4
Cache_Invalidate_All(CACHE_MAP_MASK);
#else
Cache_Invalidate_ICache_All();