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feat(spi_flash): Add exclusive support for ESP32H4

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Add 32bit addr support for esp32s31 as well
This commit is contained in:
Song Ruo Jing
2026-06-09 15:27:41 +08:00
parent 519334d640
commit c9f52c7ca7
35 changed files with 647 additions and 356 deletions
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components/esp_rom/esp32h4/include/esp32h4/rom/cache.h
+1 -1
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@@ -162,7 +162,7 @@ extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
#define CACHE_MAP_ICACHE0 BIT(0)
#define CACHE_MAP_ICACHE1 BIT(1)
#define CACHE_MAP_DCACHE BIT(4)
#define CACHE_MAP_ALL (CACHE_MAP_ICACHE0 | CACHE_MAP_ICACHE1 | CACHE_MAP_DCACHE)
#define CACHE_MAP_MASK (CACHE_MAP_ICACHE0 | CACHE_MAP_ICACHE1 | CACHE_MAP_DCACHE)
// keep the software flag same as map value
#define CACHE_AUTOLOAD_ICACHE0_FLAG BIT(0)
components/esp_rom/esp32h4/include/esp32h4/rom/opi_flash.h
+319
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@@ -0,0 +1,319 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdio.h>
#include <string.h>
#include <stdint.h>
#include <stdbool.h>
#include "spi_flash.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint16_t cmd; /*!< Command value */
uint16_t cmdBitLen; /*!< Command byte length*/
uint32_t *addr; /*!< Point to address value*/
uint32_t addrBitLen; /*!< Address byte length*/
uint32_t *txData; /*!< Point to send data buffer*/
uint32_t txDataBitLen; /*!< Send data byte length.*/
uint32_t *rxData; /*!< Point to receive data buffer*/
uint32_t rxDataBitLen; /*!< Receive Data byte length.*/
uint32_t dummyBitLen;
} esp_rom_spi_cmd_t;
typedef struct {
uint8_t mode;
uint8_t cmd_bit_len;
uint16_t cmd;
uint32_t addr;
uint8_t addr_bit_len;
uint8_t dummy_bit_len;
uint8_t data_bit_len;
uint8_t cs_sel : 4;
uint8_t is_pe : 4;
} esp_rom_opiflash_cmd_t;
typedef struct {
uint8_t addr_bit_len;
uint8_t dummy_bit_len;
uint16_t cmd;
uint8_t cmd_bit_len;
uint8_t var_dummy_en;
} esp_rom_opiflash_spi0rd_t;
typedef struct {
esp_rom_opiflash_cmd_t rdid;
esp_rom_opiflash_cmd_t rdsr;
esp_rom_opiflash_cmd_t wren;
esp_rom_opiflash_cmd_t se;
esp_rom_opiflash_cmd_t be64k;
esp_rom_opiflash_cmd_t read;
esp_rom_opiflash_cmd_t pp;
esp_rom_opiflash_spi0rd_t cache_rd_cmd;
bool usr_ecc_en;
} esp_rom_opiflash_def_t;
#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0))
#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1))
// Definition of MX25UM25645G Octa Flash
// SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
#define ESP_ROM_FLASH_PAGE_SIZE 256
// FLASH commands
#define ROM_FLASH_CMD_RDID 0x9F
#define ROM_FLASH_CMD_WRSR 0x01
#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_WREN 0x06
#define ROM_FLASH_CMD_WRDI 0x04
#define ROM_FLASH_CMD_RDSR 0x05
#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_ERASE_SEC 0x20
#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
#define ROM_FLASH_CMD_RSTEN 0x66
#define ROM_FLASH_CMD_RST 0x99
#define ROM_FLASH_CMD_SE4B 0x21
#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
#define ROM_FLASH_CMD_BE4B 0xDC
#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
#define ROM_FLASH_CMD_RST_OCT 0x6699
#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
#define ROM_FLASH_CMD_FSTRD4B 0x0C
#define ROM_FLASH_CMD_PP4B 0x12
#define ROM_FLASH_CMD_PP4B_OCT 0xED12
#define ROM_FLASH_CMD_RDID_OCT 0x609F
#define ROM_FLASH_CMD_WREN_OCT 0xF906
#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
#define ROM_FLASH_CMD_RDCR2 0x71
#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
#define ROM_FLASH_CMD_WRCR2 0x72
#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
// Definitions for GigaDevice GD25LX256E Flash
#define ROM_FLASH_CMD_RDFSR_GD 0x70
#define ROM_FLASH_CMD_RD_GD 0x03
#define ROM_FLASH_CMD_RD4B_GD 0x13
#define ROM_FLASH_CMD_FSTRD_GD 0x0B
#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
#define ROM_FLASH_CMD_PP_GD 0x02
#define ROM_FLASH_CMD_PP4B_GD 0x12
#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
#define ROM_FLASH_CMD_SE_GD 0x20
#define ROM_FLASH_CMD_SE4B_GD 0x21
#define ROM_FLASH_CMD_BE32K_GD 0x52
#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
#define ROM_FLASH_CMD_BE64K_GD 0xD8
#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
#define ROM_FLASH_CMD_EN4B_GD 0xB7
#define ROM_FLASH_CMD_DIS4B_GD 0xE9
extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def;
/**
* @brief Config the spi user command
* @param spi_num spi port
* @param pcmd pointer to accept the spi command struct
*/
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd);
/**
* @brief Start a spi user command sequence
* @param spi_num spi port
* @param rx_buf buffer pointer to receive data
* @param rx_len receive data length in byte
* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
* @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
*/
void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
/**
* @brief Config opi flash pads according to efuse settings.
*/
void esp_rom_opiflash_pin_config();
// set SPI read/write mode
/**
* @brief Set SPI operation mode
* @param spi_num spi port
* @param mode Flash Read Mode
*/
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
/**
* @brief Set data swap mode in DTR(DDR) mode
* @param spi_num spi port
* @param wr_swap to decide whether to swap fifo data in dtr write operation
* @param rd_swap to decide whether to swap fifo data in dtr read operation
*/
void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
/**
* @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
* @param spi_num spi port
*/
void esp_rom_opiflash_mode_reset(int spi_num);
/**
* @brief To execute a flash operation command
* @param spi_num spi port
* @param mode Flash Read Mode
* @param cmd data to send in command field
* @param cmd_bit_len bit length of command field
* @param addr data to send in address field
* @param addr_bit_len bit length of address field
* @param dummy_bits bit length of dummy field
* @param mosi_data data buffer to be sent in mosi field
* @param mosi_bit_len bit length of data buffer to be sent in mosi field
* @param miso_data data buffer to accept data in miso field
* @param miso_bit_len bit length of data buffer to accept data in miso field
* @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
* @param is_write_erase_operation to indicate whether this a write or erase flash operation
*/
void esp_rom_opiflash_exec_cmd(int spi_num,
esp_rom_spiflash_read_mode_t mode,
uint32_t cmd,
int cmd_bit_len,
uint32_t addr,
int addr_bit_len,
int dummy_bits,
uint8_t *mosi_data,
int mosi_bit_len,
uint8_t *miso_data,
int miso_bit_len,
uint32_t cs_mask,
bool is_write_erase_operation);
/**
* @brief send reset command to opi flash
* @param spi_num spi port
* @param mode Flash Operation Mode
*/
void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode);
/**
* @brief to read opi flash ID
* @note command format would be defined in initialization
* @param id buffer to accept id
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *id);
/**
* @brief to read opi flash status register
* @note command format would be defined in initialization
* @return opi flash status value
*/
uint8_t esp_rom_opiflash_rdsr();
/**
* @brief wait opi flash status register to be idle
* @note command format would be defined in initialization
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle();
/**
* @brief to erase flash sector
* @note command format would be defined in initialization
* @param sector_num the sector to be erased
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num);
/**
* @brief to erase flash block
* @note command format would be defined in initialization
* @param block_num the block to be erased
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num);
/**
* @brief to erase a flash area define by start address and length
* @note command format would be defined in initialization
* @param start_addr the start address to be erased
* @param area_len the erea length to be erased
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, uint32_t area_len);
/**
* @brief to read data from opi flash
* @note command format would be defined in initialization
* @param flash_addr flash address to read data from
* @param data_addr data buffer to accept the data
* @param len data length to be read
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, void *data_addr, int len);
/**
* @brief to write data to opi flash
* @note command format would be defined in initialization
* @param flash_addr flash address to write data to
* @param data_addr data buffer to write to flash
* @param len data length to write
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, void *data_addr, uint32_t len);
/**
* @brief send WREN command
* @note command format would be defined in initialization
* @return flash operation result
*/
esp_rom_spiflash_result_t esp_rom_opiflash_wren(void* arg);
/**
* @brief to configure SPI0 read flash command format for cache
* @note command format would be defined in initialization
* @param mode spi operation mode
* @cache spi0 cache read command definition
*
*/
void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache);
/**
* @brief init legacy driver for Octal Flash
*/
void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def);
#ifdef __cplusplus
}
#endif
components/esp_rom/esp32h4/include/esp32h4/rom/spi_flash.h
+1 -119
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -453,124 +453,6 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
typedef struct {
uint16_t cmd; /*!< Command value */
uint16_t cmdBitLen; /*!< Command byte length*/
uint32_t *addr; /*!< Point to address value*/
uint32_t addrBitLen; /*!< Address byte length*/
uint32_t *txData; /*!< Point to send data buffer*/
uint32_t txDataBitLen; /*!< Send data byte length.*/
uint32_t *rxData; /*!< Point to receive data buffer*/
uint32_t rxDataBitLen; /*!< Receive Data byte length.*/
uint32_t dummyBitLen;
} esp_rom_spi_cmd_t;
// Definition of MX25UM25645G Octa Flash
// SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_OP_MODE_RDCMD_DOUT 0x3B
#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000
#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000
#define ESP_ROM_FLASH_PAGE_SIZE 256
// FLASH commands
#define ROM_FLASH_CMD_RDID 0x9F
#define ROM_FLASH_CMD_WRSR 0x01
#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_WREN 0x06
#define ROM_FLASH_CMD_WRDI 0x04
#define ROM_FLASH_CMD_RDSR 0x05
#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */
#define ROM_FLASH_CMD_ERASE_SEC 0x20
#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52
#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8
#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */
#define ROM_FLASH_CMD_RSTEN 0x66
#define ROM_FLASH_CMD_RST 0x99
#define ROM_FLASH_CMD_SE4B 0x21
#define ROM_FLASH_CMD_SE4B_OCT 0xDE21
#define ROM_FLASH_CMD_BE4B 0xDC
#define ROM_FLASH_CMD_BE4B_OCT 0x23DC
#define ROM_FLASH_CMD_RSTEN_OCT 0x9966
#define ROM_FLASH_CMD_RST_OCT 0x6699
#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC
#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE
#define ROM_FLASH_CMD_FSTRD4B 0x0C
#define ROM_FLASH_CMD_PP4B 0x12
#define ROM_FLASH_CMD_PP4B_OCT 0xED12
#define ROM_FLASH_CMD_RDID_OCT 0x609F
#define ROM_FLASH_CMD_WREN_OCT 0xF906
#define ROM_FLASH_CMD_RDSR_OCT 0xFA05
#define ROM_FLASH_CMD_RDCR2 0x71
#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71
#define ROM_FLASH_CMD_WRCR2 0x72
#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72
// Definitions for GigaDevice GD25LX256E Flash
#define ROM_FLASH_CMD_RDFSR_GD 0x70
#define ROM_FLASH_CMD_RD_GD 0x03
#define ROM_FLASH_CMD_RD4B_GD 0x13
#define ROM_FLASH_CMD_FSTRD_GD 0x0B
#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C
#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B
#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C
#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB
#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC
#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD
#define ROM_FLASH_CMD_PP_GD 0x02
#define ROM_FLASH_CMD_PP4B_GD 0x12
#define ROM_FLASH_CMD_PP_OOUT_GD 0x82
#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84
#define ROM_FLASH_CMD_PP_OIO_GD 0xC2
#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E
#define ROM_FLASH_CMD_SE_GD 0x20
#define ROM_FLASH_CMD_SE4B_GD 0x21
#define ROM_FLASH_CMD_BE32K_GD 0x52
#define ROM_FLASH_CMD_BE32K4B_GD 0x5C
#define ROM_FLASH_CMD_BE64K_GD 0xD8
#define ROM_FLASH_CMD_BE64K4B_GD 0xDC
#define ROM_FLASH_CMD_EN4B_GD 0xB7
#define ROM_FLASH_CMD_DIS4B_GD 0xE9
// spi user mode command config
/**
* @brief Config the spi user command
* @param spi_num spi port
* @param pcmd pointer to accept the spi command struct
*/
void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
/**
* @brief Start a spi user command sequence
* @param spi_num spi port
* @param rx_buf buffer pointer to receive data
* @param rx_len receive data length in byte
* @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
* @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
*/
void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
// set SPI read/write mode
/**
* @brief Set SPI operation mode
* @param spi_num spi port
* @param mode Flash Read Mode
*/
void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
#ifdef __cplusplus
}
#endif
components/esp_rom/include/esp_rom_spiflash.h
+40 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,10 +12,15 @@
#include <stdbool.h>
#include "esp_rom_spiflash_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* These common types must be visible before the per-target ROM headers below,
* because those headers reference them and (re)include this header. With
* `#pragma once` the recursive include is a no-op, so the types have to be
* defined here first.
*
* Typedefs have no language linkage, so leaving them outside the `extern "C"`
* block is fine: it lets the target headers also be included outside any
* enclosing `extern "C"` (the convention for #include statements).
*/
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
@@ -47,6 +52,36 @@ typedef enum {
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/spi_flash.h"
#include "esp32p4/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/spi_flash.h"
#include "esp32c5/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C61
#include "esp32c61/rom/spi_flash.h"
#include "esp32c61/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H4
#include "esp32h4/rom/spi_flash.h"
#include "esp32h4/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S31
#include "esp32s31/rom/spi_flash.h"
#include "esp32s31/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H21
#include "esp32h21/rom/spi_flash.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
components/esp_rom/patches/esp_rom_spiflash.c
+1 -18
View File
@@ -17,23 +17,6 @@
#include "riscv/rv_utils.h"
#endif
#include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/spi_flash.h"
#include "esp32p4/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/spi_flash.h"
#include "esp32c5/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C61
#include "esp32c61/rom/spi_flash.h"
#include "esp32c61/rom/opi_flash.h"
#endif
#define SPI_IDX 1
@@ -774,7 +757,7 @@ void esp_rom_spiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const
REG_SET_BIT(SPI_MEM_C_CTRL_REG, SPI_MEM_C_Q_POL);
}
}
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4
extern void esp_rom_spi_set_address_bit_len(int spi, int addr_bits);
void esp_rom_spiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache)
{