mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-03 03:31:41 +03:00
feat(spi_flash): Add exclusive support for ESP32H4
Add 32bit addr support for esp32s31 as well
This commit is contained in:
Song Ruo Jing
@@ -31,7 +31,7 @@ extern "C" {
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#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 )
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typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
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#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (80)
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#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (32)
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/*------------------------------------------------------------------------------
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* Control
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@@ -671,10 +671,10 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
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uint8_t clock_val = 0;
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switch (PCR.mspi_conf.mspi_clk_sel) {
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case 0:
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clock_val = 48;
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clock_val = 32;
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break;
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case 1:
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clock_val = 8;
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clock_val = 20;
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break;
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case 2:
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clock_val = 64;
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -23,8 +23,6 @@
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#include <string.h>
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#include "hal/misc.h"
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//TODO: [ESP32H4] IDF-12389 inherited from verification branch, need check
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#ifdef __cplusplus
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extern "C" {
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#endif
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@@ -33,7 +31,9 @@ extern "C" {
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#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 )
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typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
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#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (80)
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#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (32)
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#define GPSPI_FLASH_LL_SUPPORT_CLK_SRC_PRE_DIV (1)
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#define GPSPI_FLASH_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
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/*------------------------------------------------------------------------------
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* Control
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@@ -45,18 +45,17 @@ typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
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*/
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static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
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{
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// dev->user.val = 0;
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// dev->ctrl.val = 0;
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dev->user.val = 0;
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dev->ctrl.val = 0;
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// dev->clk_gate.clk_en = 1;
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// dev->clk_gate.mst_clk_active = 1;
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// dev->clk_gate.mst_clk_sel = 1;
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dev->clk_gate.clk_en = 1;
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dev->clk_gate.mst_clk_active = 1;
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dev->clk_gate.mst_clk_sel = 1;
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// dev->dma_conf.val = 0;
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// dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
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// dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
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// dev->dma_conf.dma_slv_seg_trans_en = 0;
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abort();
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dev->dma_conf.val = 0;
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dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
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dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
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dev->dma_conf.dma_slv_seg_trans_en = 0;
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}
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/**
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@@ -68,8 +67,7 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
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*/
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static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
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{
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// return (dev->cmd.usr == 0);
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abort();
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return (dev->cmd.usr == 0);
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}
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/**
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@@ -81,21 +79,20 @@ static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
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*/
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static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
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{
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// if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
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// // If everything is word-aligned, do a faster memcpy
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// memcpy(buffer, (void *)dev->data_buf, read_len);
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// } else {
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// // Otherwise, slow(er) path copies word by word
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// int copy_len = read_len;
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// for (int i = 0; i < (read_len + 3) / 4; i++) {
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// int word_len = MIN(sizeof(uint32_t), copy_len);
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// uint32_t word = dev->data_buf[i].buf;
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// memcpy(buffer, &word, word_len);
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// buffer = (void *)((intptr_t)buffer + word_len);
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// copy_len -= word_len;
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// }
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// }
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abort();
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if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
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// If everything is word-aligned, do a faster memcpy
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memcpy(buffer, (void *)dev->data_buf, read_len);
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} else {
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// Otherwise, slow(er) path copies word by word
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int copy_len = read_len;
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for (int i = 0; i < (read_len + 3) / 4; i++) {
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int word_len = MIN(sizeof(uint32_t), copy_len);
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uint32_t word = dev->data_buf[i].buf;
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memcpy(buffer, &word, word_len);
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buffer = (void *)((intptr_t)buffer + word_len);
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copy_len -= word_len;
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}
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}
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}
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/**
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@@ -106,8 +103,7 @@ static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer,
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*/
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static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
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{
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// dev->data_buf[0].buf = word;
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abort();
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dev->data_buf[0].buf = word;
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}
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/**
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@@ -119,17 +115,16 @@ static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
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*/
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static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
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{
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// // Load data registers, word at a time
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// int num_words = (length + 3) / 4;
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// for (int i = 0; i < num_words; i++) {
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// uint32_t word = 0;
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// uint32_t word_len = MIN(length, sizeof(word));
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// memcpy(&word, buffer, word_len);
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// dev->data_buf[i].buf = word;
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// length -= word_len;
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// buffer = (void *)((intptr_t)buffer + word_len);
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// }
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abort();
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// Load data registers, word at a time
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int num_words = (length + 3) / 4;
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for (int i = 0; i < num_words; i++) {
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uint32_t word = 0;
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uint32_t word_len = MIN(length, sizeof(word));
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memcpy(&word, buffer, word_len);
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dev->data_buf[i].buf = word;
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length -= word_len;
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buffer = (void *)((intptr_t)buffer + word_len);
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}
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}
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/**
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@@ -141,10 +136,9 @@ static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *bu
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*/
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static inline void gpspi_flash_ll_user_start(spi_dev_t *dev, bool pe_ops)
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{
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// dev->cmd.update = 1;
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// while (dev->cmd.update);
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// dev->cmd.usr = 1;
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abort();
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dev->cmd.update = 1;
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while (dev->cmd.update);
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dev->cmd.usr = 1;
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}
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/**
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@@ -164,8 +158,7 @@ static inline void gpspi_flash_ll_set_pe_bit(spi_dev_t *dev)
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*/
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static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
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{
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// dev->ctrl.hold_pol = pol_val;
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abort();
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dev->ctrl.hold_pol = pol_val;
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}
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/**
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@@ -177,8 +170,7 @@ static inline void gpspi_flash_ll_set_hold_pol(spi_dev_t *dev, uint32_t pol_val)
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*/
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static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
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{
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// return dev->cmd.usr == 0;
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abort();
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return dev->cmd.usr == 0;
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}
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/**
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@@ -188,14 +180,13 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
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*/
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static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
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{
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// typeof (dev->user) user = {
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// .usr_mosi = 0,
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// .usr_miso = 1,
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// .usr_addr = 1,
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// .usr_command = 1,
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// };
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// dev->user.val = user.val;
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abort();
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typeof(dev->user) user = {
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.usr_mosi = 0,
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.usr_miso = 1,
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.usr_addr = 1,
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.usr_command = 1,
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};
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dev->user.val = user.val;
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}
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/*------------------------------------------------------------------------------
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* Configs
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@@ -208,9 +199,8 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
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*/
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static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
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{
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// dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
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// dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
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abort();
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dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
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dev->misc.cs1_dis = (pin == 1) ? 0 : 1;
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}
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/**
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@@ -221,44 +211,43 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
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*/
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static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
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{
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// typeof (dev->ctrl) ctrl;
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// ctrl.val = dev->ctrl.val;
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// typeof (dev->user) user;
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// user.val = dev->user.val;
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typeof(dev->ctrl) ctrl;
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ctrl.val = dev->ctrl.val;
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typeof(dev->user) user;
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user.val = dev->user.val;
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// ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
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// user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
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ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
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user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M);
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// switch (read_mode) {
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// case SPI_FLASH_FASTRD:
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// //the default option
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// case SPI_FLASH_SLOWRD:
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// break;
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// case SPI_FLASH_QIO:
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// ctrl.fread_quad = 1;
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// ctrl.faddr_quad = 1;
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// user.fwrite_quad = 1;
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// break;
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// case SPI_FLASH_QOUT:
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// ctrl.fread_quad = 1;
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// user.fwrite_quad = 1;
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// break;
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// case SPI_FLASH_DIO:
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// ctrl.fread_dual = 1;
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// ctrl.faddr_dual = 1;
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// user.fwrite_dual = 1;
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// break;
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// case SPI_FLASH_DOUT:
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// ctrl.fread_dual = 1;
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// user.fwrite_dual = 1;
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// break;
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// default:
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// abort();
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// }
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switch (read_mode) {
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case SPI_FLASH_FASTRD:
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//the default option
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case SPI_FLASH_SLOWRD:
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break;
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case SPI_FLASH_QIO:
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ctrl.fread_quad = 1;
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ctrl.faddr_quad = 1;
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user.fwrite_quad = 1;
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break;
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case SPI_FLASH_QOUT:
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ctrl.fread_quad = 1;
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user.fwrite_quad = 1;
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break;
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case SPI_FLASH_DIO:
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ctrl.fread_dual = 1;
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ctrl.faddr_dual = 1;
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user.fwrite_dual = 1;
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break;
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case SPI_FLASH_DOUT:
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ctrl.fread_dual = 1;
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user.fwrite_dual = 1;
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break;
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default:
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abort();
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}
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// dev->ctrl.val = ctrl.val;
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// dev->user.val = user.val;
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abort();
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dev->ctrl.val = ctrl.val;
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dev->user.val = user.val;
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}
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/**
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@@ -269,8 +258,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
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*/
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static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock_reg_t *clock_val)
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{
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// dev->clock.val = *clock_val;
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abort();
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dev->clock.val = *clock_val;
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}
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/**
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@@ -281,11 +269,10 @@ static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock
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*/
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static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
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{
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// dev->user.usr_miso = bitlen > 0;
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// if (bitlen) {
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// dev->ms_dlen.ms_data_bitlen = bitlen - 1;
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// }
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abort();
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dev->user.usr_miso = bitlen > 0;
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if (bitlen) {
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dev->ms_dlen.ms_data_bitlen = bitlen - 1;
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}
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}
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/**
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@@ -297,11 +284,10 @@ static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitle
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*/
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static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
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{
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// dev->user.usr_mosi = bitlen > 0;
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// if (bitlen) {
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// dev->ms_dlen.ms_data_bitlen = bitlen - 1;
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// }
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abort();
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dev->user.usr_mosi = bitlen > 0;
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if (bitlen) {
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dev->ms_dlen.ms_data_bitlen = bitlen - 1;
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}
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}
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/**
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@@ -313,13 +299,12 @@ static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitle
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*/
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static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen)
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{
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// dev->user.usr_command = 1;
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// typeof(dev->user2) user2 = {
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// .usr_command_value = command,
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// .usr_command_bitlen = (bitlen - 1),
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// };
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// dev->user2.val = user2.val;
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abort();
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dev->user.usr_command = 1;
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typeof(dev->user2) user2 = {
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.usr_command_value = command,
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.usr_command_bitlen = (bitlen - 1),
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};
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dev->user2.val = user2.val;
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}
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/**
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@@ -330,8 +315,7 @@ static inline void gpspi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, u
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*/
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static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
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{
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// return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
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abort();
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return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
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}
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/**
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@@ -342,9 +326,8 @@ static inline int gpspi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
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*/
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static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
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{
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// dev->user1.usr_addr_bitlen = (bitlen - 1);
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// dev->user.usr_addr = bitlen ? 1 : 0;
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abort();
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dev->user1.usr_addr_bitlen = (bitlen - 1);
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dev->user.usr_addr = bitlen ? 1 : 0;
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}
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/**
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@@ -356,9 +339,8 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle
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static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
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{
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// The blank region should be all ones
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// uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
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// dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
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abort();
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uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
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dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
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}
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/**
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@@ -369,8 +351,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
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*/
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static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
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{
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// dev->addr.val = addr;
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abort();
|
||||
dev->addr.val = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -381,9 +362,10 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
|
||||
*/
|
||||
static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
|
||||
{
|
||||
// dev->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
|
||||
abort();
|
||||
dev->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
if (dummy_n > 0) {
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -395,10 +377,9 @@ static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
|
||||
*/
|
||||
static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev)
|
||||
{
|
||||
// dev->ctrl.dummy_out = out_en;
|
||||
// dev->ctrl.q_pol = out_lev;
|
||||
// dev->ctrl.d_pol = out_lev;
|
||||
abort();
|
||||
dev->ctrl.dummy_out = out_en;
|
||||
dev->ctrl.q_pol = out_lev;
|
||||
dev->ctrl.d_pol = out_lev;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -409,16 +390,24 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
|
||||
*/
|
||||
static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
|
||||
{
|
||||
// dev->user1.cs_hold_time = hold_n - 1;
|
||||
// dev->user.cs_hold = (hold_n > 0? 1: 0);
|
||||
abort();
|
||||
dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
|
||||
if (hold_n > 0) {
|
||||
dev->user1.cs_hold_time = hold_n - 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the delay of SPI clocks before the first SPI clock after the CS active edge.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
|
||||
*/
|
||||
static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
|
||||
{
|
||||
// dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
|
||||
// dev->user1.cs_setup_time = cs_setup_time - 1;
|
||||
abort();
|
||||
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
|
||||
if (cs_setup_time > 0) {
|
||||
dev->user1.cs_setup_time = cs_setup_time - 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -430,31 +419,39 @@ static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup
|
||||
*/
|
||||
static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
|
||||
{
|
||||
// uint32_t div_parameter;
|
||||
// // See comments of `clock` in `spi_struct.h`
|
||||
// if (clkdiv == 1) {
|
||||
// div_parameter = (1 << 31);
|
||||
// } else {
|
||||
// div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12));
|
||||
// }
|
||||
// return div_parameter;
|
||||
abort();
|
||||
uint32_t div_parameter;
|
||||
// See comments of `clock` in `spi_struct.h`
|
||||
if (clkdiv == 1) {
|
||||
div_parameter = (1 << 31);
|
||||
} else {
|
||||
div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12));
|
||||
}
|
||||
return div_parameter;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
|
||||
{
|
||||
int clock_id = 0;
|
||||
switch (clk_source) {
|
||||
case SPI_CLK_SRC_RC_FAST:
|
||||
PCR.spi2_clkm_conf.spi2_clkm_sel = 2;
|
||||
clock_id = 2;
|
||||
break;
|
||||
case SPI_CLK_SRC_XTAL:
|
||||
PCR.spi2_clkm_conf.spi2_clkm_sel = 0;
|
||||
clock_id = 0;
|
||||
break;
|
||||
default:
|
||||
PCR.spi2_clkm_conf.spi2_clkm_sel = 1;
|
||||
default: // PLL_F48M
|
||||
clock_id = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (hw == &GPSPI2) {
|
||||
PCR.spi2_clkm_conf.spi2_clkm_sel = clock_id;
|
||||
} else if (hw == &GPSPI3) {
|
||||
PCR.spi3_clkm_conf.spi3_clkm_sel = clock_id;
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -465,8 +462,31 @@ static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source
|
||||
*/
|
||||
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
|
||||
{
|
||||
(void) hw;
|
||||
PCR.spi2_clkm_conf.spi2_clkm_en = enable;
|
||||
if (hw == &GPSPI2) {
|
||||
PCR.spi2_clkm_conf.spi2_clkm_en = enable;
|
||||
} else if (hw == &GPSPI3) {
|
||||
PCR.spi3_clkm_conf.spi3_clkm_en = enable;
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable SPI flash module clock
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param enable true to enable, false to disable
|
||||
*/
|
||||
static inline void gpspi_flash_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div)
|
||||
{
|
||||
(void) hs_div;
|
||||
if (hw == &GPSPI2) {
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.spi2_clkm_conf, spi2_clkm_div_num, mst_div - 1);
|
||||
} else if (hw == &GPSPI3) {
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.spi3_clkm_conf, spi3_clkm_div_num, mst_div - 1);
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
#include "soc/spi_mem_struct.h"
|
||||
#include "soc/spi_mem_reg.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
#include "rom/spi_flash.h"
|
||||
#include "rom/opi_flash.h"
|
||||
#include "hal/psram_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -35,7 +35,8 @@ extern "C" {
|
||||
}\
|
||||
dev_id; \
|
||||
})
|
||||
// Since ESP32-C6, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
|
||||
#define SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL (1)
|
||||
// WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
|
||||
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8)
|
||||
|
||||
typedef union {
|
||||
@@ -68,6 +69,7 @@ typedef union {
|
||||
#define spi_flash_ll_set_hold(dev, hold_n) gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
|
||||
#define spi_flash_ll_set_cs_setup(dev, cs_setup_time) gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
|
||||
#define spi_flash_ll_set_extra_address(dev, extra_addr) { /* Not supported on gpspi on ESP32-H4*/ }
|
||||
#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enale) { /* Not supported on gpspi on ESP32-H4*/ }
|
||||
#else
|
||||
#define spi_flash_ll_reset(dev) spimem_flash_ll_reset((spi_mem_dev_t*)dev)
|
||||
#define spi_flash_ll_cmd_is_done(dev) spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
|
||||
@@ -101,6 +103,7 @@ typedef union {
|
||||
#define spi_flash_ll_sync_reset() spimem_flash_ll_sync_reset()
|
||||
#define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
|
||||
#define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg) spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
|
||||
#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enale) spimem_flash_ll_wb_mode_enable((spi_mem_dev_t*)dev, wb_mode_enale)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -60,6 +60,7 @@ static inline void spimem_flash_ll_reset(spi_mem_dev_t *dev)
|
||||
*
|
||||
* @return true if last command is done, otherwise false.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline bool spimem_flash_ll_cmd_is_done(const spi_mem_dev_t *dev)
|
||||
{
|
||||
return (dev->cmd.val == 0);
|
||||
@@ -374,6 +375,7 @@ static inline void spimem_flash_ll_exit_dpd(spi_mem_dev_t *dev)
|
||||
* @param buffer Buffer to hold the output data
|
||||
* @param read_len Length to get out of the buffer
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buffer, uint32_t read_len)
|
||||
{
|
||||
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
|
||||
@@ -399,6 +401,7 @@ static inline void spimem_flash_ll_get_buffer_data(spi_mem_dev_t *dev, void *buf
|
||||
* @param buffer Buffer holding the data
|
||||
* @param length Length of data in bytes.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_buffer_data(spi_mem_dev_t *dev, const void *buffer, uint32_t length)
|
||||
{
|
||||
// Load data registers, word at a time
|
||||
@@ -435,6 +438,7 @@ static inline void spimem_flash_ll_program_page(spi_mem_dev_t *dev, const void *
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param pe_ops Is page program/erase operation or not.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev, bool pe_ops)
|
||||
{
|
||||
uint32_t usr_pe = (pe_ops ? 0x60000 : 0x40000);
|
||||
@@ -538,6 +542,7 @@ static inline void spimem_flash_ll_set_clock(spi_mem_dev_t *dev, spimem_flash_ll
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of input, in bits.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_miso = bitlen > 0;
|
||||
@@ -551,6 +556,7 @@ static inline void spimem_flash_ll_set_miso_bitlen(spi_mem_dev_t *dev, uint32_t
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of output, in bits.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_mosi = bitlen > 0;
|
||||
@@ -564,6 +570,7 @@ static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t
|
||||
* @param command Command to send
|
||||
* @param bitlen Length of the command
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_command = 1;
|
||||
@@ -588,8 +595,10 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of the address, in bits
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->cache_fctrl.usr_addr_4byte = (bitlen == 32) ? 1 : 0;
|
||||
dev->user1.usr_addr_bitlen = (bitlen - 1);
|
||||
dev->user.usr_addr = bitlen ? 1 : 0;
|
||||
}
|
||||
@@ -602,8 +611,19 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
|
||||
*/
|
||||
static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
|
||||
{
|
||||
dev->cache_fctrl.usr_addr_4byte = 0;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
|
||||
dev->rd_status.wb_mode_bitlen = 7; // 8 - 1
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable extra address for bits M0-M7 in DIO/QIO mode.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param wb_mode_enable true for enabling wb_mode
|
||||
*/
|
||||
static inline void spimem_flash_ll_wb_mode_enable(spi_mem_dev_t *dev, bool wb_mode_enable)
|
||||
{
|
||||
dev->rd_status.wb_mode_en = wb_mode_enable;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -623,6 +643,7 @@ static inline void spimem_flash_ll_set_address(spi_mem_dev_t *dev, uint32_t addr
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param addr Address to send
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t addr, uint32_t bitlen)
|
||||
{
|
||||
(void)bitlen;
|
||||
@@ -635,10 +656,13 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param dummy_n Cycles of dummy phases
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
|
||||
{
|
||||
dev->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
|
||||
if (dummy_n > 0) {
|
||||
dev->user1.usr_dummy_cyclelen = dummy_n - 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -652,6 +676,12 @@ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
|
||||
//not supported on esp32h4
|
||||
}
|
||||
|
||||
/**
|
||||
* Set CS setup time
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param cs_setup_time CS setup time
|
||||
*/
|
||||
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
|
||||
{
|
||||
//not supported on esp32h4
|
||||
@@ -670,10 +700,10 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
|
||||
uint8_t clock_val = 0;
|
||||
switch (PCR.mspi_clk_conf.mspi_func_clk_sel) {
|
||||
case 0:
|
||||
clock_val = 48;
|
||||
clock_val = 32;
|
||||
break;
|
||||
case 1:
|
||||
clock_val = 8;
|
||||
clock_val = 20;
|
||||
break;
|
||||
case 2:
|
||||
clock_val = 64;
|
||||
@@ -711,6 +741,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
|
||||
|
||||
* @param level 1: 1: output high, 0: output low
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level)
|
||||
{
|
||||
dev->ctrl.wp_reg = level;
|
||||
@@ -747,6 +778,7 @@ static inline void spimem_flash_ll_sync_reset(void)
|
||||
* @param user1_reg user1_reg
|
||||
* @param user2_reg user2_reg
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
|
||||
{
|
||||
*ctrl_reg = dev->ctrl.val;
|
||||
@@ -763,6 +795,7 @@ static inline void spimem_flash_ll_get_common_command_register_info(spi_mem_dev_
|
||||
* @param user1_reg user1_reg
|
||||
* @param user2_reg user2_reg
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
|
||||
{
|
||||
dev->ctrl.val = ctrl_reg;
|
||||
|
||||
@@ -35,7 +35,7 @@ extern "C" {
|
||||
}\
|
||||
dev_id; \
|
||||
})
|
||||
// Since ESP32-P4, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
|
||||
// WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
|
||||
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (8)
|
||||
|
||||
typedef union {
|
||||
|
||||
Reference in New Issue
Block a user