soc: create abstraction for cpu related operations

components/xtensa/esp32s2/include/xtensa/config/extreg.h

@@ -0,0 +1,21 @@
+/*
+ * ESP32-S2 External Register symbolic names
+ */
+
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define DSRSET 0x10200C

components/xtensa/esp32s2/include/xtensa/config/specreg.h

@@ -44,6 +44,7 @@
 #define DBREAKA_1	145
 #define DBREAKC_0	160
 #define DBREAKC_1	161
+#define CONFIGID0	176
 #define EPC_1		177
 #define EPC_2		178
 #define EPC_3		179
@@ -58,6 +59,7 @@
 #define EPS_5		197
 #define EPS_6		198
 #define EPS_7		199
+#define CONFIGID1	208
 #define EXCSAVE_1	209
 #define EXCSAVE_2	210
 #define EXCSAVE_3	211