diff --git a/components/esp_hal_gpio/esp32s31/sdm_periph.c b/components/esp_hal_gpio/esp32s31/sdm_periph.c index 375d70fe8e5..9bab401cebd 100644 --- a/components/esp_hal_gpio/esp32s31/sdm_periph.c +++ b/components/esp_hal_gpio/esp32s31/sdm_periph.c @@ -53,7 +53,7 @@ static const regdma_entries_config_t gpio_ext_regdma_entries[] = { // backup stage: save configuration and status registers // restore stage: restore the configuration and status registers [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPIO_EXT_LINK(0x00), + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_SDM_LINK(0x00), GPIO_EXT_RETENTION_REGS_BASE, GPIO_EXT_RETENTION_REGS_BASE, GPIO_EXT_RETENTION_REGS_CNT, 0, 0, gpio_ext_regs_map[0], gpio_ext_regs_map[1], diff --git a/components/esp_hal_pmu/esp32s31/include/hal/pau_ll.h b/components/esp_hal_pmu/esp32s31/include/hal/pau_ll.h new file mode 100644 index 00000000000..87f4ed0a617 --- /dev/null +++ b/components/esp_hal_pmu/esp32s31/include/hal/pau_ll.h @@ -0,0 +1,129 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-S31 PAU(Power Assist Unit) register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/pau_reg.h" +#include "soc/pau_struct.h" +#include "soc/hp_sys_clkrst_struct.h" +#include "soc/lp_system_struct.h" +#include "hal/pau_types.h" +#include "hal/assert.h" +#include "hal/misc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void pau_ll_enable_bus_clock(bool enable) +{ + if (enable) { + HP_SYS_CLKRST.regdma_ctrl0.reg_regdma_sys_clk_en = 1; + HP_SYS_CLKRST.regdma_ctrl0.reg_regdma_rst_en = 0; + } else { + HP_SYS_CLKRST.regdma_ctrl0.reg_regdma_sys_clk_en = 0; + HP_SYS_CLKRST.regdma_ctrl0.reg_regdma_rst_en = 1; + } +} + +static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) +{ + return dev->regdma_conf.flow_err; +} + +static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link) +{ + dev->regdma_conf.link_sel = link; +} + +static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ + dev->regdma_conf.to_mem = to_mem ? 1 : 0; +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev, bool enable) +{ + dev->regdma_conf.start = enable; +} + +static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) +{ + dev->regdma_conf.sel_mac = 1; +} + +static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev) +{ + dev->regdma_conf.sel_mac = 0; +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ + dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0; +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev) +{ + dev->regdma_conf.start_mac = 1; +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev) +{ + dev->regdma_conf.start_mac = 0; +} + +static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev) +{ + return dev->regdma_current_link_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev) +{ + return dev->regdma_peri_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev) +{ + return dev->regdma_mem_addr.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev) +{ + return dev->int_raw.val; +} + +static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) +{ + return dev->int_st.val; +} + +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev, bool enable) +{ + dev->int_ena.done_int_ena = enable; +} + +static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable) +{ + dev->int_ena.error_int_ena = enable; +} + +static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) +{ + dev->int_clr.done_int_clr = 1; +} + +static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) +{ + dev->int_clr.error_int_clr = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_pmu/esp32s31/pau_hal.c b/components/esp_hal_pmu/esp32s31/pau_hal.c new file mode 100644 index 00000000000..fc1e4c610d9 --- /dev/null +++ b/components/esp_hal_pmu/esp32s31/pau_hal.c @@ -0,0 +1,78 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/pau_hal.h" +#include "hal/lp_sys_ll.h" +#include "hal/pau_types.h" + +void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) +{ + lp_sys_ll_set_pau_link_addr((uint32_t)(*link_addr)[0]); +} + +void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + pau_ll_set_regdma_select_wifimac_link(hal->dev); + pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_wifimac_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_deselect_wifimac_link(hal->dev); + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + /* The link 3 of REGDMA is reserved, we use it as an extra linked list to + * provide backup and restore services for BLE, IEEE802.15.4 and possibly + * other modules. + * It is also used as software trigger REGDMA to backup and restore, and is + * used by the UT to test module driver retention function. + */ + pau_ll_select_regdma_entry_link(hal->dev, 3); + pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, true); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev, false); + pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +#if SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE +void pau_hal_regdma_link_count_config(pau_hal_context_t *hal, int count) +{ + HAL_ASSERT(count > 0); + lp_sys_set_regdma_link_count(count - 1); +} +#endif + +void pau_hal_set_regdma_work_timeout(pau_hal_context_t *hal, uint32_t loop_num, uint32_t time) +{ + HAL_ASSERT(loop_num > 0 && time > 0); + lp_sys_ll_set_pau_link_work_tout_thres(loop_num); + lp_sys_ll_set_pau_link_backup_tout_thres(time); +} + +void pau_hal_set_regdma_wait_timeout(pau_hal_context_t *hal, int count, int interval) +{ + HAL_ASSERT(count > 0 && interval > 0); + lp_sys_ll_set_pau_link_wait_tout_thres(count); + lp_sys_ll_set_pau_reg_read_interval(interval); +} diff --git a/components/esp_hal_timg/esp32s31/timer_periph.c b/components/esp_hal_timg/esp32s31/timer_periph.c index 0024dcda9e2..308c0935889 100644 --- a/components/esp_hal_timg/esp32s31/timer_periph.c +++ b/components/esp_hal_timg/esp32s31/timer_periph.c @@ -33,7 +33,7 @@ const soc_timg_gptimer_signal_desc_t soc_timg_gptimer_signals[2][2] = { } }; -#if SOC_PAU_SUPPORTED +#if SOC_PAU_SUPPORTED && SOC_TIMER_SUPPORT_SLEEP_RETENTION /* Registers in retention context: * TIMG_T0CONFIG_REG * TIMG_T0ALARMLO_REG diff --git a/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c new file mode 100644 index 00000000000..e5f8db29723 --- /dev/null +++ b/components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c @@ -0,0 +1,127 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_private/sleep_clock.h" +#include "soc/hp_sys_clkrst_reg.h" +#include "soc/pmu_reg.h" +#include "soc/lp_peri_clkrst_reg.h" +#include "pmu_bit_defs.h" +#include "modem/modem_syscon_reg.h" +#include "modem/modem_lpcon_reg.h" + +ESP_LOG_ATTR_TAG(TAG, "sleep_clock"); + +esp_err_t sleep_clock_system_retention_init(void *arg) +{ + #define N_REGS_PCR() (((HP_SYS_CLKRST_CLK_EN0_REG - DR_REG_HP_SYS_CLKRST_BASE) / 4) + 1) + + const static sleep_retention_entries_config_t pcr_regs_retention[] = { + /* Enable i2c master clock */ + [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), LP_PERICLKRST_I2CMST_CTRL_REG, LP_PERICLKRST_LP_I2CMST_CLK_EN, LP_PERICLKRST_LP_I2CMST_CLK_EN_M, 1, 0), .owner = ENTRY(0) }, + /* Start SYSPLL self-calibration */ + [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, 0, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) }, + /* Wait calibration done */ + [2] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(2), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M, 1, 0), .owner = ENTRY(0) }, + /* Stop SYSPLL self-calibration */ + [3] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(3), HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M, 1, 0), .owner = ENTRY(0) }, + /* Clock configuration retention */ + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(4), DR_REG_HP_SYS_CLKRST_BASE, DR_REG_HP_SYS_CLKRST_BASE, N_REGS_PCR(), 0, 0), .owner = ENTRY(0) }, /* pcr */ + [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + [8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(8), HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG, 0x0, HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M, 1, 0), .owner = ENTRY(0) }, + }; + + esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for system (PCR) retention"); + ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization"); + return ESP_OK; + + #undef N_REGS_PCR +} + +#if CONFIG_MAC_BB_PD || CONFIG_BTDM_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE +#include "rom/ets_sys.h" +esp_err_t sleep_clock_modem_retention_init(void *arg) +{ + #define N_REGS_SYSCON() (((MODEM_SYSCON_MEM_RF2_CONF_REG - MODEM_SYSCON_TEST_CONF_REG) / 4) + 1) + #define N_REGS_LPCON() (((MODEM_LPCON_MODEM_INTR_STATUS_REG - MODEM_LPCON_TEST_CONF_REG) / 4) + 1) + const static sleep_retention_entries_config_t modem_regs_retention[] = { + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MODEMSYSCON_LINK(0), 0x20109c30, 0xf, 0xffffffff, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMSYSCON_LINK(1), MODEM_SYSCON_TEST_CONF_REG, MODEM_SYSCON_TEST_CONF_REG, 12, 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEMLPCON_LINK(0), MODEM_LPCON_TEST_CONF_REG, MODEM_LPCON_TEST_CONF_REG, N_REGS_LPCON(), 0, 0), .owner = ENTRY(0) | ENTRY(1) }, /* MODEM SYSCON */ + }; + + esp_err_t err = sleep_retention_entries_create(modem_regs_retention, ARRAY_SIZE(modem_regs_retention), REGDMA_LINK_PRI_MODEM_CLK, SLEEP_RETENTION_MODULE_CLOCK_MODEM); + ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (SYSCON) retention, 1 level priority"); + ESP_LOGI(TAG, "Modem Power, Clock and Reset sleep retention initialization"); + return ESP_OK; + + #undef N_REGS_SYSCON +} +#endif + +bool clock_domain_pd_allowed(void) +{ + const sleep_retention_module_bitmap_t inited_modules = sleep_retention_get_inited_modules(); + const sleep_retention_module_bitmap_t created_modules = sleep_retention_get_created_modules(); + const sleep_retention_module_bitmap_t sys_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap[SLEEP_RETENTION_MODULE_SYS_PERIPH >> 5] = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH % 32) }; +/* The clock and reset of MODEM (WiFi, BLE and 15.4) modules are managed + * through MODEM_SYSCON, when one or more MODEMs are initialized, it is + * necessary to check the state of CLOCK_MODEM to determine MODEM domain on + * or off. The clock and reset of digital peripherals are managed through + * PCR, with TOP domain similar to MODEM domain. */ + __attribute__((unused)) sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; +#if SOC_WIFI_SUPPORTED + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC % 32); + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_BB % 32); +#endif +#if SOC_BT_SUPPORTED + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BLE_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_BLE_MAC % 32); + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BT_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_BT_BB % 32); +#endif +#if SOC_IEEE802154_SUPPORTED + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_802154_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_802154_MAC % 32); + modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_BT_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_BT_BB % 32); +#endif + + const sleep_retention_module_bitmap_t null_module = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; + + sleep_retention_module_bitmap_t mask = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; + const sleep_retention_module_bitmap_t system_modules = sleep_retention_module_bitmap_and(inited_modules, sys_clk_dep_modules); + if (!sleep_retention_module_bitmap_eq(system_modules, null_module)) { + mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_SYSTEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM % 32); + } + + #if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED || SOC_IEEE802154_SUPPORTED + const sleep_retention_module_bitmap_t modem_modules = sleep_retention_module_bitmap_and(inited_modules, modem_clk_dep_modules); + if (!sleep_retention_module_bitmap_eq(modem_modules, null_module)) { + mask.bitmap[SLEEP_RETENTION_MODULE_CLOCK_MODEM >> 5] |= BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM % 32); + } +#endif + + const sleep_retention_module_bitmap_t clock_domain_inited_modules = sleep_retention_module_bitmap_and(inited_modules, mask); + const sleep_retention_module_bitmap_t clock_domain_created_modules = sleep_retention_module_bitmap_and(created_modules, mask); + return sleep_retention_module_bitmap_eq(clock_domain_inited_modules, clock_domain_created_modules); +} + +ESP_SYSTEM_INIT_FN(sleep_clock_startup_init, SECONDARY, BIT(0), 106) +{ + sleep_retention_module_init_param_t init_param = { + .cbs = { .create = { .handle = sleep_clock_system_retention_init, .arg = NULL } }, + .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE + }; + sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM, &init_param); + +#if CONFIG_MAC_BB_PD || CONFIG_BTDM_CTRL_SLEEP_ENABLE || CONFIG_IEEE802154_SLEEP_ENABLE + init_param = (sleep_retention_module_init_param_t) { + .cbs = { .create = { .handle = sleep_clock_modem_retention_init, .arg = NULL } }, + .attribute = SLEEP_RETENTION_MODULE_ATTR_PASSIVE + }; + sleep_retention_module_init(SLEEP_RETENTION_MODULE_CLOCK_MODEM, &init_param); +#endif + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c b/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c new file mode 100644 index 00000000000..5b7ce3919ab --- /dev/null +++ b/components/esp_hw_support/port/esp32s31/peripheral_domain_pd.c @@ -0,0 +1,98 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "sdkconfig.h" +#include "soc/system_periph_retention.h" +#include "esp_private/sleep_retention.h" + +bool peripheral_domain_pd_allowed(void) +{ +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP + const sleep_retention_module_bitmap_t inited_modules = sleep_retention_get_inited_modules(); + const sleep_retention_module_bitmap_t created_modules = sleep_retention_get_created_modules(); + + sleep_retention_module_bitmap_t mask = RETENTION_MODULE_BITMAP_INIT(NULL); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_SYS_PERIPH); + // ESP32S31 supports WDT sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG0_WDT); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG1_WDT); + + // ESP32S31 supports Timer sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG0_TIMER0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG0_TIMER1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG1_TIMER0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TG1_TIMER1); + + // ESP32S31 supports AHB_DMA sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH2); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH3); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AHB_DMA_CH4); + + // ESP32S31 supports AXI_DMA sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_AXI_DMA_CH2); + + // ESP32S31 supports UART sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART2); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_UART3); + + // ESP32S31 supports RMT sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_RMT0); + + // ESP32S31 supports PAU and I2S sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2S0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2S1); + + // ESP32S31 supports I2C sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2C0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_I2C1); + + // ESP32S31 supports ETM sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_ETM0); + + // ESP32S31 supports TWAI sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TWAI0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_TWAI1); + + // ESP32S31 supports PARLIO sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_PARLIO0); + + // ESP32S31 supports GPSPI2 sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GPSPI2); + // ESP32S31 supports GPSPI3 sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_GPSPI3); + + // ESP32S31 supports LEDC sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_LEDC0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_LEDC1); + + // ESP32S31 supports MCPWM sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM1); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM2); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_MCPWM3); + + // ESP32S31 supports PCNT sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_PCNT0); + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_PCNT1); + + // ESP32S31 supports SDM sleep retention + RETENTION_MODULE_BITMAP_SET(&mask, SLEEP_RETENTION_MODULE_SDM0); + + const sleep_retention_module_bitmap_t peripheral_domain_inited_modules = sleep_retention_module_bitmap_and(inited_modules, mask); + const sleep_retention_module_bitmap_t peripheral_domain_created_modules = sleep_retention_module_bitmap_and(created_modules, mask); + return sleep_retention_module_bitmap_eq(peripheral_domain_inited_modules, peripheral_domain_created_modules); +#else + return false; +#endif +} diff --git a/components/esp_hw_support/sleep_gpio.c b/components/esp_hw_support/sleep_gpio.c index 4e50ddc0875..4d01436d8d1 100644 --- a/components/esp_hw_support/sleep_gpio.c +++ b/components/esp_hw_support/sleep_gpio.c @@ -239,7 +239,9 @@ void esp_deep_sleep_wakeup_io_reset(void) if ((rtc_io_mask & BIT(rtcio_num)) == 0) { continue; } +#if SOC_RTCIO_HOLD_SUPPORTED rtcio_hal_hold_disable(rtcio_num); +#endif rtc_io_mask &= ~BIT(rtcio_num); } #endif diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index f2e5b7faed0..ef8473c4dfb 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -2154,8 +2154,10 @@ static void ext1_wakeup_prepare(void) rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_DIGITAL); // set input enable gpio_ll_input_enable(&GPIO, gpio); +#if SOC_RTCIO_HOLD_SUPPORTED // hold rtc_pin to use it during sleep state rtcio_hal_hold_enable(rtc_pin); +#endif #endif // Keep track of pins which are processed to bail out early rtc_gpio_mask &= ~BIT(rtc_pin); diff --git a/components/esp_system/int_wdt.c b/components/esp_system/int_wdt.c index 0a98483286f..3a43caf2035 100644 --- a/components/esp_system/int_wdt.c +++ b/components/esp_system/int_wdt.c @@ -24,7 +24,7 @@ #include "esp_private/periph_ctrl.h" #include "esp_private/esp_int_wdt.h" -#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TIMER_SUPPORT_SLEEP_RETENTION +#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_MWDT_SUPPORT_SLEEP_RETENTION #include "esp_private/sleep_retention.h" #endif diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt index d1388091b3e..26e07b8e552 100644 --- a/components/esp_system/system_init_fn.txt +++ b/components/esp_system/system_init_fn.txt @@ -93,6 +93,7 @@ SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/p SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h21/sleep_clock.c on BIT(0) SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32h4/sleep_clock.c on BIT(0) SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c on BIT(0) +SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32s31/sleep_clock.c on BIT(0) SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0) # app_trace doesn't have init dependencies diff --git a/components/hal/esp32s31/include/hal/lp_sys_ll.h b/components/hal/esp32s31/include/hal/lp_sys_ll.h index ee8ac11b7fd..bee101c9e9d 100644 --- a/components/hal/esp32s31/include/hal/lp_sys_ll.h +++ b/components/hal/esp32s31/include/hal/lp_sys_ll.h @@ -35,14 +35,13 @@ FORCE_INLINE_ATTR void lp_sys_ll_inform_wakeup_type(bool dslp) } } -FORCE_INLINE_ATTR void lp_sys_ll_set_pau_aon_bypass(bool bypass) -{ - LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0; -} - -FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout) +FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_wait_tout_thres(uint32_t tout) { LP_SYS.backup_dma_cfg1.link_wait_tout_thres_aon = tout; +} + +FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_work_tout_thres(uint32_t tout) +{ LP_SYS.backup_dma_cfg1.link_work_tout_thres_aon = tout; } @@ -61,6 +60,11 @@ FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_addr(uint32_t addr) LP_SYS.backup_dma_cfg2.link_addr_aon = addr; } +static inline void lp_sys_set_regdma_link_count(int count) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_SYS.backup_dma_cfg1, branch_link_length_aon, count); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/etm_periph.h b/components/hal/include/hal/etm_periph.h index c4c79408900..cdaa6c6bbde 100644 --- a/components/hal/include/hal/etm_periph.h +++ b/components/hal/include/hal/etm_periph.h @@ -22,7 +22,7 @@ extern "C" { #endif -#if SOC_HAS(PAU) +#if SOC_HAS(PAU) && SOC_ETM_SUPPORT_SLEEP_RETENTION typedef struct { periph_retention_module_t module; // ID of the ETM as a retention module diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h index 6382ad901d9..3bc72fa0bb7 100644 --- a/components/soc/esp32c5/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c5/include/soc/retention_periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -16,39 +16,39 @@ extern "C" { typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MIN = 0, SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ - /* clock module, which includes system and modem */ + /* clock module */ SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */ - SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + SLEEP_RETENTION_MODULE_SYS_PERIPH = 2, /* Timer Group by target*/ - SLEEP_RETENTION_MODULE_TG0_WDT = 4, - SLEEP_RETENTION_MODULE_TG1_WDT = 5, - SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, - SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + SLEEP_RETENTION_MODULE_TG0_WDT = 3, + SLEEP_RETENTION_MODULE_TG1_WDT = 4, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 6, /* GDMA by channel */ - SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, - SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, - SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, + SLEEP_RETENTION_MODULE_GDMA_CH0 = 7, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 8, + SLEEP_RETENTION_MODULE_GDMA_CH2 = 9, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_ADC = 11, - SLEEP_RETENTION_MODULE_I2C0 = 12, - SLEEP_RETENTION_MODULE_RMT0 = 13, - SLEEP_RETENTION_MODULE_UART0 = 14, - SLEEP_RETENTION_MODULE_UART1 = 15, - SLEEP_RETENTION_MODULE_I2S0 = 16, - SLEEP_RETENTION_MODULE_ETM0 = 17, - SLEEP_RETENTION_MODULE_TEMP_SENSOR = 18, - SLEEP_RETENTION_MODULE_PARLIO0 = 19, - SLEEP_RETENTION_MODULE_GPSPI2 = 20, - SLEEP_RETENTION_MODULE_LEDC = 21, - SLEEP_RETENTION_MODULE_MCPWM0 = 22, - SLEEP_RETENTION_MODULE_SDM0 = 23, - SLEEP_RETENTION_MODULE_TWAI0 = 24, - SLEEP_RETENTION_MODULE_TWAI1 = 25, + SLEEP_RETENTION_MODULE_ADC = 10, + SLEEP_RETENTION_MODULE_I2C0 = 11, + SLEEP_RETENTION_MODULE_RMT0 = 12, + SLEEP_RETENTION_MODULE_UART0 = 13, + SLEEP_RETENTION_MODULE_UART1 = 14, + SLEEP_RETENTION_MODULE_I2S0 = 15, + SLEEP_RETENTION_MODULE_ETM0 = 16, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 17, + SLEEP_RETENTION_MODULE_PARLIO0 = 18, + SLEEP_RETENTION_MODULE_GPSPI2 = 19, + SLEEP_RETENTION_MODULE_LEDC = 20, + SLEEP_RETENTION_MODULE_MCPWM0 = 21, + SLEEP_RETENTION_MODULE_SDM0 = 22, + SLEEP_RETENTION_MODULE_TWAI0 = 23, + SLEEP_RETENTION_MODULE_TWAI1 = 24, /* modem module, which includes WiFi, BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 25, SLEEP_RETENTION_MODULE_WIFI_MAC = 26, SLEEP_RETENTION_MODULE_WIFI_BB = 27, SLEEP_RETENTION_MODULE_BLE_MAC = 28, @@ -59,34 +59,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; -#define is_top_domain_module(m) \ - ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI1) ? true \ - : false) +#define is_top_domain_module(m) (m <= SLEEP_RETENTION_MODULE_SDM0) #ifdef __cplusplus } diff --git a/components/soc/esp32c6/include/soc/retention_periph_defs.h b/components/soc/esp32c6/include/soc/retention_periph_defs.h index 6326a1dbccf..6a17ad6ccfc 100644 --- a/components/soc/esp32c6/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c6/include/soc/retention_periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -16,39 +16,39 @@ extern "C" { typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MIN = 0, SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ - /* clock module, which includes system and modem */ + /* clock module */ SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */ - SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + SLEEP_RETENTION_MODULE_SYS_PERIPH = 2, /* Timer Group by target*/ - SLEEP_RETENTION_MODULE_TG0_WDT = 4, - SLEEP_RETENTION_MODULE_TG1_WDT = 5, - SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, - SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + SLEEP_RETENTION_MODULE_TG0_WDT = 3, + SLEEP_RETENTION_MODULE_TG1_WDT = 4, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 6, /* GDMA by channel */ - SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, - SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, - SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, + SLEEP_RETENTION_MODULE_GDMA_CH0 = 7, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 8, + SLEEP_RETENTION_MODULE_GDMA_CH2 = 9, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_ADC = 11, - SLEEP_RETENTION_MODULE_I2C0 = 12, - SLEEP_RETENTION_MODULE_RMT0 = 13, - SLEEP_RETENTION_MODULE_UART0 = 14, - SLEEP_RETENTION_MODULE_UART1 = 15, - SLEEP_RETENTION_MODULE_I2S0 = 16, - SLEEP_RETENTION_MODULE_ETM0 = 17, - SLEEP_RETENTION_MODULE_TEMP_SENSOR = 18, - SLEEP_RETENTION_MODULE_TWAI0 = 19, - SLEEP_RETENTION_MODULE_TWAI1 = 20, - SLEEP_RETENTION_MODULE_PARLIO0 = 21, - SLEEP_RETENTION_MODULE_GPSPI2 = 22, - SLEEP_RETENTION_MODULE_LEDC = 23, - SLEEP_RETENTION_MODULE_MCPWM0 = 24, - SLEEP_RETENTION_MODULE_SDM0 = 25, + SLEEP_RETENTION_MODULE_ADC = 10, + SLEEP_RETENTION_MODULE_I2C0 = 11, + SLEEP_RETENTION_MODULE_RMT0 = 12, + SLEEP_RETENTION_MODULE_UART0 = 13, + SLEEP_RETENTION_MODULE_UART1 = 14, + SLEEP_RETENTION_MODULE_I2S0 = 15, + SLEEP_RETENTION_MODULE_ETM0 = 16, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 17, + SLEEP_RETENTION_MODULE_TWAI0 = 18, + SLEEP_RETENTION_MODULE_TWAI1 = 19, + SLEEP_RETENTION_MODULE_PARLIO0 = 20, + SLEEP_RETENTION_MODULE_GPSPI2 = 21, + SLEEP_RETENTION_MODULE_LEDC = 22, + SLEEP_RETENTION_MODULE_MCPWM0 = 23, + SLEEP_RETENTION_MODULE_SDM0 = 24, /* Modem module, which includes WiFi, BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 25, SLEEP_RETENTION_MODULE_WIFI_MAC = 26, SLEEP_RETENTION_MODULE_WIFI_BB = 27, SLEEP_RETENTION_MODULE_BLE_MAC = 28, @@ -58,33 +58,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; -#define is_top_domain_module(m) \ - ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \ - : false) +#define is_top_domain_module(m) (m <= SLEEP_RETENTION_MODULE_SDM0) #ifdef __cplusplus } diff --git a/components/soc/esp32c61/include/soc/retention_periph_defs.h b/components/soc/esp32c61/include/soc/retention_periph_defs.h index 6310404be04..1db16def943 100644 --- a/components/soc/esp32c61/include/soc/retention_periph_defs.h +++ b/components/soc/esp32c61/include/soc/retention_periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -16,32 +16,32 @@ extern "C" { typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MIN = 0, SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ - /* clock module, which includes system and modem */ + /* clock module */ SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, IOMUX, SPIMEM, SysTimer, etc.. */ - SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + SLEEP_RETENTION_MODULE_SYS_PERIPH = 2, /* Timer Group by target */ - SLEEP_RETENTION_MODULE_TG0_WDT = 4, - SLEEP_RETENTION_MODULE_TG1_WDT = 5, - SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, - SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + SLEEP_RETENTION_MODULE_TG0_WDT = 3, + SLEEP_RETENTION_MODULE_TG1_WDT = 4, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 6, /* GDMA by channel */ - SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, - SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, + SLEEP_RETENTION_MODULE_GDMA_CH0 = 7, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 8, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_I2C0 = 12, - SLEEP_RETENTION_MODULE_UART0 = 14, - SLEEP_RETENTION_MODULE_UART1 = 15, - SLEEP_RETENTION_MODULE_UART2 = 16, - SLEEP_RETENTION_MODULE_ETM0 = 17, - SLEEP_RETENTION_MODULE_GPSPI2 = 18, - SLEEP_RETENTION_MODULE_LEDC = 19, - SLEEP_RETENTION_MODULE_I2S0 = 20, - SLEEP_RETENTION_MODULE_TEMP_SENSOR = 21, + SLEEP_RETENTION_MODULE_I2C0 = 9, + SLEEP_RETENTION_MODULE_UART0 = 10, + SLEEP_RETENTION_MODULE_UART1 = 11, + SLEEP_RETENTION_MODULE_UART2 = 12, + SLEEP_RETENTION_MODULE_ETM0 = 13, + SLEEP_RETENTION_MODULE_GPSPI2 = 14, + SLEEP_RETENTION_MODULE_LEDC = 15, + SLEEP_RETENTION_MODULE_I2S0 = 16, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 17, /* Modem module, which includes WiFi, BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 25, SLEEP_RETENTION_MODULE_WIFI_MAC = 26, SLEEP_RETENTION_MODULE_WIFI_BB = 27, SLEEP_RETENTION_MODULE_BLE_MAC = 28, @@ -51,26 +51,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; -#define is_top_domain_module(m) \ - ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ - : false) +#define is_top_domain_module(m) (m <= SLEEP_RETENTION_MODULE_TEMP_SENSOR) #ifdef __cplusplus } diff --git a/components/soc/esp32h2/include/soc/retention_periph_defs.h b/components/soc/esp32h2/include/soc/retention_periph_defs.h index 1464ef07837..d8d21b5d9a0 100644 --- a/components/soc/esp32h2/include/soc/retention_periph_defs.h +++ b/components/soc/esp32h2/include/soc/retention_periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -16,39 +16,39 @@ extern "C" { typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MIN = 0, SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ - /* clock module, which includes system and modem */ + /* clock module */ SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */ - SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + SLEEP_RETENTION_MODULE_SYS_PERIPH = 2, /* Timer Group by target*/ - SLEEP_RETENTION_MODULE_TG0_WDT = 4, - SLEEP_RETENTION_MODULE_TG1_WDT = 5, - SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, - SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + SLEEP_RETENTION_MODULE_TG0_WDT = 3, + SLEEP_RETENTION_MODULE_TG1_WDT = 4, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 6, /* GDMA by channel */ - SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, - SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, - SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, + SLEEP_RETENTION_MODULE_GDMA_CH0 = 7, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 8, + SLEEP_RETENTION_MODULE_GDMA_CH2 = 9, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_ADC = 11, - SLEEP_RETENTION_MODULE_I2C0 = 12, - SLEEP_RETENTION_MODULE_I2C1 = 13, - SLEEP_RETENTION_MODULE_RMT0 = 14, - SLEEP_RETENTION_MODULE_UART0 = 15, - SLEEP_RETENTION_MODULE_UART1 = 16, - SLEEP_RETENTION_MODULE_I2S0 = 17, - SLEEP_RETENTION_MODULE_ETM0 = 18, - SLEEP_RETENTION_MODULE_TEMP_SENSOR = 19, - SLEEP_RETENTION_MODULE_TWAI0 = 20, - SLEEP_RETENTION_MODULE_PARLIO0 = 21, - SLEEP_RETENTION_MODULE_GPSPI2 = 22, - SLEEP_RETENTION_MODULE_LEDC = 23, - SLEEP_RETENTION_MODULE_MCPWM0 = 24, - SLEEP_RETENTION_MODULE_SDM0 = 25, + SLEEP_RETENTION_MODULE_ADC = 10, + SLEEP_RETENTION_MODULE_I2C0 = 11, + SLEEP_RETENTION_MODULE_I2C1 = 12, + SLEEP_RETENTION_MODULE_RMT0 = 13, + SLEEP_RETENTION_MODULE_UART0 = 14, + SLEEP_RETENTION_MODULE_UART1 = 15, + SLEEP_RETENTION_MODULE_I2S0 = 16, + SLEEP_RETENTION_MODULE_ETM0 = 17, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 18, + SLEEP_RETENTION_MODULE_TWAI0 = 19, + SLEEP_RETENTION_MODULE_PARLIO0 = 20, + SLEEP_RETENTION_MODULE_GPSPI2 = 21, + SLEEP_RETENTION_MODULE_LEDC = 22, + SLEEP_RETENTION_MODULE_MCPWM0 = 23, + SLEEP_RETENTION_MODULE_SDM0 = 24, /* Modem module, which includes BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 26, SLEEP_RETENTION_MODULE_BLE_MAC = 28, SLEEP_RETENTION_MODULE_BT_BB = 29, SLEEP_RETENTION_MODULE_802154_MAC = 30, @@ -56,33 +56,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; -#define is_top_domain_module(m) \ - ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \ - : false) +#define is_top_domain_module(m) ((m) <= SLEEP_RETENTION_MODULE_SDM0) #ifdef __cplusplus } diff --git a/components/soc/esp32h21/include/soc/retention_periph_defs.h b/components/soc/esp32h21/include/soc/retention_periph_defs.h index 1464ef07837..d8d21b5d9a0 100644 --- a/components/soc/esp32h21/include/soc/retention_periph_defs.h +++ b/components/soc/esp32h21/include/soc/retention_periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -16,39 +16,39 @@ extern "C" { typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MIN = 0, SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ - /* clock module, which includes system and modem */ + /* clock module */ SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */ - SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + SLEEP_RETENTION_MODULE_SYS_PERIPH = 2, /* Timer Group by target*/ - SLEEP_RETENTION_MODULE_TG0_WDT = 4, - SLEEP_RETENTION_MODULE_TG1_WDT = 5, - SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, - SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + SLEEP_RETENTION_MODULE_TG0_WDT = 3, + SLEEP_RETENTION_MODULE_TG1_WDT = 4, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 6, /* GDMA by channel */ - SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, - SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, - SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, + SLEEP_RETENTION_MODULE_GDMA_CH0 = 7, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 8, + SLEEP_RETENTION_MODULE_GDMA_CH2 = 9, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_ADC = 11, - SLEEP_RETENTION_MODULE_I2C0 = 12, - SLEEP_RETENTION_MODULE_I2C1 = 13, - SLEEP_RETENTION_MODULE_RMT0 = 14, - SLEEP_RETENTION_MODULE_UART0 = 15, - SLEEP_RETENTION_MODULE_UART1 = 16, - SLEEP_RETENTION_MODULE_I2S0 = 17, - SLEEP_RETENTION_MODULE_ETM0 = 18, - SLEEP_RETENTION_MODULE_TEMP_SENSOR = 19, - SLEEP_RETENTION_MODULE_TWAI0 = 20, - SLEEP_RETENTION_MODULE_PARLIO0 = 21, - SLEEP_RETENTION_MODULE_GPSPI2 = 22, - SLEEP_RETENTION_MODULE_LEDC = 23, - SLEEP_RETENTION_MODULE_MCPWM0 = 24, - SLEEP_RETENTION_MODULE_SDM0 = 25, + SLEEP_RETENTION_MODULE_ADC = 10, + SLEEP_RETENTION_MODULE_I2C0 = 11, + SLEEP_RETENTION_MODULE_I2C1 = 12, + SLEEP_RETENTION_MODULE_RMT0 = 13, + SLEEP_RETENTION_MODULE_UART0 = 14, + SLEEP_RETENTION_MODULE_UART1 = 15, + SLEEP_RETENTION_MODULE_I2S0 = 16, + SLEEP_RETENTION_MODULE_ETM0 = 17, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 18, + SLEEP_RETENTION_MODULE_TWAI0 = 19, + SLEEP_RETENTION_MODULE_PARLIO0 = 20, + SLEEP_RETENTION_MODULE_GPSPI2 = 21, + SLEEP_RETENTION_MODULE_LEDC = 22, + SLEEP_RETENTION_MODULE_MCPWM0 = 23, + SLEEP_RETENTION_MODULE_SDM0 = 24, /* Modem module, which includes BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 26, SLEEP_RETENTION_MODULE_BLE_MAC = 28, SLEEP_RETENTION_MODULE_BT_BB = 29, SLEEP_RETENTION_MODULE_802154_MAC = 30, @@ -56,33 +56,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; -#define is_top_domain_module(m) \ - ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \ - : false) +#define is_top_domain_module(m) ((m) <= SLEEP_RETENTION_MODULE_SDM0) #ifdef __cplusplus } diff --git a/components/soc/esp32h4/include/soc/retention_periph_defs.h b/components/soc/esp32h4/include/soc/retention_periph_defs.h index cd2713fcfba..d58f6bd8f58 100644 --- a/components/soc/esp32h4/include/soc/retention_periph_defs.h +++ b/components/soc/esp32h4/include/soc/retention_periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -16,43 +16,43 @@ extern "C" { typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MIN = 0, SLEEP_RETENTION_MODULE_NULL = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ - /* clock module, which includes system and modem */ + /* clock module */ SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1, - SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2, /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */ - SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + SLEEP_RETENTION_MODULE_SYS_PERIPH = 2, /* Timer Group by target*/ - SLEEP_RETENTION_MODULE_TG0_WDT = 4, - SLEEP_RETENTION_MODULE_TG1_WDT = 5, - SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, - SLEEP_RETENTION_MODULE_TG1_TIMER0 = 7, + SLEEP_RETENTION_MODULE_TG0_WDT = 3, + SLEEP_RETENTION_MODULE_TG1_WDT = 4, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 5, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 6, /* GDMA by channel */ - SLEEP_RETENTION_MODULE_GDMA_CH0 = 8, - SLEEP_RETENTION_MODULE_GDMA_CH1 = 9, - SLEEP_RETENTION_MODULE_GDMA_CH2 = 10, - SLEEP_RETENTION_MODULE_GDMA_CH3 = 11, - SLEEP_RETENTION_MODULE_GDMA_CH4 = 12, + SLEEP_RETENTION_MODULE_GDMA_CH0 = 7, + SLEEP_RETENTION_MODULE_GDMA_CH1 = 8, + SLEEP_RETENTION_MODULE_GDMA_CH2 = 9, + SLEEP_RETENTION_MODULE_GDMA_CH3 = 10, + SLEEP_RETENTION_MODULE_GDMA_CH4 = 11, /* MISC Peripherals */ - SLEEP_RETENTION_MODULE_ADC = 13, - SLEEP_RETENTION_MODULE_I2C0 = 14, - SLEEP_RETENTION_MODULE_I2C1 = 15, - SLEEP_RETENTION_MODULE_RMT0 = 16, - SLEEP_RETENTION_MODULE_UART0 = 17, - SLEEP_RETENTION_MODULE_UART1 = 18, - SLEEP_RETENTION_MODULE_I2S0 = 19, - SLEEP_RETENTION_MODULE_ETM0 = 20, - SLEEP_RETENTION_MODULE_TEMP_SENSOR = 21, - SLEEP_RETENTION_MODULE_TWAI0 = 22, - SLEEP_RETENTION_MODULE_PARLIO0 = 23, - SLEEP_RETENTION_MODULE_GPSPI2 = 24, - SLEEP_RETENTION_MODULE_GPSPI3 = 25, - SLEEP_RETENTION_MODULE_LEDC = 26, - SLEEP_RETENTION_MODULE_MCPWM0 = 27, - SLEEP_RETENTION_MODULE_MCPWM1 = 28, - SLEEP_RETENTION_MODULE_SDM0 = 29, + SLEEP_RETENTION_MODULE_ADC = 12, + SLEEP_RETENTION_MODULE_I2C0 = 13, + SLEEP_RETENTION_MODULE_I2C1 = 14, + SLEEP_RETENTION_MODULE_RMT0 = 15, + SLEEP_RETENTION_MODULE_UART0 = 16, + SLEEP_RETENTION_MODULE_UART1 = 17, + SLEEP_RETENTION_MODULE_I2S0 = 18, + SLEEP_RETENTION_MODULE_ETM0 = 19, + SLEEP_RETENTION_MODULE_TEMP_SENSOR = 20, + SLEEP_RETENTION_MODULE_TWAI0 = 21, + SLEEP_RETENTION_MODULE_PARLIO0 = 22, + SLEEP_RETENTION_MODULE_GPSPI2 = 23, + SLEEP_RETENTION_MODULE_GPSPI3 = 24, + SLEEP_RETENTION_MODULE_LEDC = 25, + SLEEP_RETENTION_MODULE_MCPWM0 = 26, + SLEEP_RETENTION_MODULE_MCPWM1 = 27, + SLEEP_RETENTION_MODULE_SDM0 = 28, /* Modem module, which includes BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 29, SLEEP_RETENTION_MODULE_BLE_MAC = 30, SLEEP_RETENTION_MODULE_BT_BB = 31, SLEEP_RETENTION_MODULE_802154_MAC = 32, @@ -60,37 +60,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; -#define is_top_domain_module(m) \ - ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH3) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GDMA_CH4) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ADC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TEMP_SENSOR) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI3) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \ - : false) +#define is_top_domain_module(m) ((m) <= SLEEP_RETENTION_MODULE_SDM0) #ifdef __cplusplus } diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h index 1a6d3685a98..bfa1570a712 100644 --- a/components/soc/esp32p4/include/soc/retention_periph_defs.h +++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -67,47 +67,7 @@ typedef enum periph_retention_module { SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 } periph_retention_module_t; -#define is_top_domain_module(m) \ - ( ((m) == SLEEP_RETENTION_MODULE_NULL) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SYS_PERIPH) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_WDT) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG0_TIMER1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TG1_TIMER1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_AHB_DMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_AHB_DMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_AHB_DMA_CH2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_AXI_DMA_CH0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_AXI_DMA_CH1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_AXI_DMA_CH2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART3) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_UART4) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2S2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_I2C1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_ETM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_TWAI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_GPSPI3) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_MCPWM1) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_JPEG) ? true \ - : ((m) == SLEEP_RETENTION_MODULE_LCDCAM) ? true \ - : false) +#define is_top_domain_module(m) (m <= SLEEP_RETENTION_MODULE_LCDCAM) #ifdef __cplusplus } diff --git a/components/soc/esp32s31/include/modem/modem_lpcon_reg.h b/components/soc/esp32s31/include/modem/modem_lpcon_reg.h new file mode 100644 index 00000000000..e5113d6aef6 --- /dev/null +++ b/components/soc/esp32s31/include/modem/modem_lpcon_reg.h @@ -0,0 +1,543 @@ +/** + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif +#include "reg_base.h" + +#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) +/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_EN (BIT(0)) +#define MODEM_LPCON_CLK_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_EN_V 0x1 +#define MODEM_LPCON_CLK_EN_S 0 + +#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) +/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) +/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) +/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 + +#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) +/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2)) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1 +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 +/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003 +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S)) +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3 +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0 + +#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) +/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) +#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 +#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 + +#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) +/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 +/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 +/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_V 0x1 +#define MODEM_LPCON_CLK_COEX_EN_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 + +#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) +/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1 +#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 +/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 +/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 +#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 +/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_V 0x1 +#define MODEM_LPCON_CLK_COEX_FO_S 1 +/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) +#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 + +#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) +/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 +/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 +/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) +#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 +/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 + +#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) +/* MODEM_LPCON_RST_DCMEM : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_DCMEM (BIT(4)) +#define MODEM_LPCON_RST_DCMEM_M (BIT(4)) +#define MODEM_LPCON_RST_DCMEM_V 0x1 +#define MODEM_LPCON_RST_DCMEM_S 4 +/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_V 0x1 +#define MODEM_LPCON_RST_LP_TIMER_S 3 +/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_I2C_MST (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_V 0x1 +#define MODEM_LPCON_RST_I2C_MST_S 2 +/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_COEX (BIT(1)) +#define MODEM_LPCON_RST_COEX_M (BIT(1)) +#define MODEM_LPCON_RST_COEX_V 0x1 +#define MODEM_LPCON_RST_COEX_S 1 +/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_RST_WIFIPWR (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) +#define MODEM_LPCON_RST_WIFIPWR_V 0x1 +#define MODEM_LPCON_RST_WIFIPWR_S 0 + +#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) +/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)) +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0 + +#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) +/* MODEM_LPCON_CFR_MEM_FORCE : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_CFR_MEM_FORCE (BIT(27)) +#define MODEM_LPCON_CFR_MEM_FORCE_M (BIT(27)) +#define MODEM_LPCON_CFR_MEM_FORCE_V 0x1 +#define MODEM_LPCON_CFR_MEM_FORCE_S 27 +/* MODEM_LPCON_CFR_MEM_MODE : R/W ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CFR_MEM_MODE 0x00000007 +#define MODEM_LPCON_CFR_MEM_MODE_M ((MODEM_LPCON_CFR_MEM_MODE_V)<<(MODEM_LPCON_CFR_MEM_MODE_S)) +#define MODEM_LPCON_CFR_MEM_MODE_V 0x7 +#define MODEM_LPCON_CFR_MEM_MODE_S 24 +/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 +/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007 +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)) +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7 +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 +/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1 +#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 +/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007 +#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S)) +#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7 +#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 +/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) +#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15)) +#define MODEM_LPCON_BC_MEM_FORCE_V 0x1 +#define MODEM_LPCON_BC_MEM_FORCE_S 15 +/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_BC_MEM_MODE 0x00000007 +#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S)) +#define MODEM_LPCON_BC_MEM_MODE_V 0x7 +#define MODEM_LPCON_BC_MEM_MODE_S 12 +/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) +#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11)) +#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1 +#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 +/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007 +#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S)) +#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7 +#define MODEM_LPCON_PBUS_MEM_MODE_S 8 +/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) +#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7)) +#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1 +#define MODEM_LPCON_AGC_MEM_FORCE_S 7 +/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_MODE 0x00000007 +#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S)) +#define MODEM_LPCON_AGC_MEM_MODE_V 0x7 +#define MODEM_LPCON_AGC_MEM_MODE_S 4 +/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) +#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3)) +#define MODEM_LPCON_DC_MEM_FORCE_V 0x1 +#define MODEM_LPCON_DC_MEM_FORCE_S 3 +/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_DC_MEM_MODE 0x00000007 +#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S)) +#define MODEM_LPCON_DC_MEM_MODE_V 0x7 +#define MODEM_LPCON_DC_MEM_MODE_S 0 + +#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) +/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)) +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0 + +#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) +/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)) +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0 + +#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) +/* MODEM_LPCON_PWR_MEM_BASE : R/W ;bitpos:[19:4] ;default: 16'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_PWR_MEM_BASE 0x0000FFFF +#define MODEM_LPCON_PWR_MEM_BASE_M ((MODEM_LPCON_PWR_MEM_BASE_V)<<(MODEM_LPCON_PWR_MEM_BASE_S)) +#define MODEM_LPCON_PWR_MEM_BASE_V 0xFFFF +#define MODEM_LPCON_PWR_MEM_BASE_S 4 +/* MODEM_LPCON_CFR_MEM_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CFR_MEM_EN (BIT(3)) +#define MODEM_LPCON_CFR_MEM_EN_M (BIT(3)) +#define MODEM_LPCON_CFR_MEM_EN_V 0x1 +#define MODEM_LPCON_CFR_MEM_EN_S 3 +/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) +#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2)) +#define MODEM_LPCON_AGC_MEM_EN_V 0x1 +#define MODEM_LPCON_AGC_MEM_EN_S 2 +/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) +#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1)) +#define MODEM_LPCON_PBUS_MEM_EN_V 0x1 +#define MODEM_LPCON_PBUS_MEM_EN_S 1 +/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0)) +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0)) +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0 + +#define MODEM_LPCON_DCMEM_VALID_0_REG (DR_REG_MODEM_LPCON_BASE + 0x3C) +/* MODEM_LPCON_DCMEM_VALID_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_DCMEM_VALID_0 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_0_M ((MODEM_LPCON_DCMEM_VALID_0_V)<<(MODEM_LPCON_DCMEM_VALID_0_S)) +#define MODEM_LPCON_DCMEM_VALID_0_V 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_0_S 0 + +#define MODEM_LPCON_DCMEM_VALID_1_REG (DR_REG_MODEM_LPCON_BASE + 0x40) +/* MODEM_LPCON_DCMEM_VALID_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_DCMEM_VALID_1 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_1_M ((MODEM_LPCON_DCMEM_VALID_1_V)<<(MODEM_LPCON_DCMEM_VALID_1_S)) +#define MODEM_LPCON_DCMEM_VALID_1_V 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_1_S 0 + +#define MODEM_LPCON_DCMEM_VALID_2_REG (DR_REG_MODEM_LPCON_BASE + 0x44) +/* MODEM_LPCON_DCMEM_VALID_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_DCMEM_VALID_2 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_2_M ((MODEM_LPCON_DCMEM_VALID_2_V)<<(MODEM_LPCON_DCMEM_VALID_2_S)) +#define MODEM_LPCON_DCMEM_VALID_2_V 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_2_S 0 + +#define MODEM_LPCON_DCMEM_VALID_3_REG (DR_REG_MODEM_LPCON_BASE + 0x48) +/* MODEM_LPCON_DCMEM_VALID_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_DCMEM_VALID_3 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_3_M ((MODEM_LPCON_DCMEM_VALID_3_V)<<(MODEM_LPCON_DCMEM_VALID_3_S)) +#define MODEM_LPCON_DCMEM_VALID_3_V 0xFFFFFFFF +#define MODEM_LPCON_DCMEM_VALID_3_S 0 + +#define MODEM_LPCON_MODEM_INTR_WAKEUP_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4C) +/* MODEM_LPCON_BT_MAC_INT1_WAKEUP_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BT_MAC_INT1_WAKEUP_EN (BIT(13)) +#define MODEM_LPCON_BT_MAC_INT1_WAKEUP_EN_M (BIT(13)) +#define MODEM_LPCON_BT_MAC_INT1_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_BT_MAC_INT1_WAKEUP_EN_S 13 +/* MODEM_LPCON_ZB_MAC_INTR_WAKEUP_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_ZB_MAC_INTR_WAKEUP_EN (BIT(12)) +#define MODEM_LPCON_ZB_MAC_INTR_WAKEUP_EN_M (BIT(12)) +#define MODEM_LPCON_ZB_MAC_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_ZB_MAC_INTR_WAKEUP_EN_S 12 +/* MODEM_LPCON_I2C_MST_INTR_WAKEUP_EN : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_I2C_MST_INTR_WAKEUP_EN (BIT(11)) +#define MODEM_LPCON_I2C_MST_INTR_WAKEUP_EN_M (BIT(11)) +#define MODEM_LPCON_I2C_MST_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_I2C_MST_INTR_WAKEUP_EN_S 11 +/* MODEM_LPCON_BLE_SEC_INTR_WAKEUP_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BLE_SEC_INTR_WAKEUP_EN (BIT(10)) +#define MODEM_LPCON_BLE_SEC_INTR_WAKEUP_EN_M (BIT(10)) +#define MODEM_LPCON_BLE_SEC_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_BLE_SEC_INTR_WAKEUP_EN_S 10 +/* MODEM_LPCON_BLE_TIMER_INTR_WAKEUP_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BLE_TIMER_INTR_WAKEUP_EN (BIT(9)) +#define MODEM_LPCON_BLE_TIMER_INTR_WAKEUP_EN_M (BIT(9)) +#define MODEM_LPCON_BLE_TIMER_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_BLE_TIMER_INTR_WAKEUP_EN_S 9 +/* MODEM_LPCON_COEX_INTR_WAKEUP_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_COEX_INTR_WAKEUP_EN (BIT(8)) +#define MODEM_LPCON_COEX_INTR_WAKEUP_EN_M (BIT(8)) +#define MODEM_LPCON_COEX_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_COEX_INTR_WAKEUP_EN_S 8 +/* MODEM_LPCON_LP_TIMER_INTR_WAKEUP_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_LP_TIMER_INTR_WAKEUP_EN (BIT(7)) +#define MODEM_LPCON_LP_TIMER_INTR_WAKEUP_EN_M (BIT(7)) +#define MODEM_LPCON_LP_TIMER_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_LP_TIMER_INTR_WAKEUP_EN_S 7 +/* MODEM_LPCON_BT_BB_NMI_WAKEUP_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BT_BB_NMI_WAKEUP_EN (BIT(6)) +#define MODEM_LPCON_BT_BB_NMI_WAKEUP_EN_M (BIT(6)) +#define MODEM_LPCON_BT_BB_NMI_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_BT_BB_NMI_WAKEUP_EN_S 6 +/* MODEM_LPCON_BT_BB_INTR_WAKEUP_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BT_BB_INTR_WAKEUP_EN (BIT(5)) +#define MODEM_LPCON_BT_BB_INTR_WAKEUP_EN_M (BIT(5)) +#define MODEM_LPCON_BT_BB_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_BT_BB_INTR_WAKEUP_EN_S 5 +/* MODEM_LPCON_BT_MAC_INTR_WAKEUP_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_BT_MAC_INTR_WAKEUP_EN (BIT(4)) +#define MODEM_LPCON_BT_MAC_INTR_WAKEUP_EN_M (BIT(4)) +#define MODEM_LPCON_BT_MAC_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_BT_MAC_INTR_WAKEUP_EN_S 4 +/* MODEM_LPCON_WIFI_BB_INTR_WAKEUP_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_WIFI_BB_INTR_WAKEUP_EN (BIT(3)) +#define MODEM_LPCON_WIFI_BB_INTR_WAKEUP_EN_M (BIT(3)) +#define MODEM_LPCON_WIFI_BB_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_WIFI_BB_INTR_WAKEUP_EN_S 3 +/* MODEM_LPCON_WIFI_PWR_INTR_WAKEUP_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_WIFI_PWR_INTR_WAKEUP_EN (BIT(2)) +#define MODEM_LPCON_WIFI_PWR_INTR_WAKEUP_EN_M (BIT(2)) +#define MODEM_LPCON_WIFI_PWR_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_WIFI_PWR_INTR_WAKEUP_EN_S 2 +/* MODEM_LPCON_WIFI_MAC_NMI_WAKEUP_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_WIFI_MAC_NMI_WAKEUP_EN (BIT(1)) +#define MODEM_LPCON_WIFI_MAC_NMI_WAKEUP_EN_M (BIT(1)) +#define MODEM_LPCON_WIFI_MAC_NMI_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_WIFI_MAC_NMI_WAKEUP_EN_S 1 +/* MODEM_LPCON_WIFI_MAC_INTR_WAKEUP_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_LPCON_WIFI_MAC_INTR_WAKEUP_EN (BIT(0)) +#define MODEM_LPCON_WIFI_MAC_INTR_WAKEUP_EN_M (BIT(0)) +#define MODEM_LPCON_WIFI_MAC_INTR_WAKEUP_EN_V 0x1 +#define MODEM_LPCON_WIFI_MAC_INTR_WAKEUP_EN_S 0 + +#define MODEM_LPCON_MODEM_INTR_STATUS_REG (DR_REG_MODEM_LPCON_BASE + 0x50) +/* MODEM_LPCON_MODEM_INTR_VECTOR : RO ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: .*/ +#define MODEM_LPCON_MODEM_INTR_VECTOR 0x00003FFF +#define MODEM_LPCON_MODEM_INTR_VECTOR_M ((MODEM_LPCON_MODEM_INTR_VECTOR_V)<<(MODEM_LPCON_MODEM_INTR_VECTOR_S)) +#define MODEM_LPCON_MODEM_INTR_VECTOR_V 0x3FFF +#define MODEM_LPCON_MODEM_INTR_VECTOR_S 0 + +#define MODEM_LPCON_MEM_CONF2_REG (DR_REG_MODEM_LPCON_BASE + 0x54) +/* MODEM_LPCON_PWR_MEM_MODE_SEL : R/W ;bitpos:[3:0] ;default: 4'b0100 ; */ +/*description: .*/ +#define MODEM_LPCON_PWR_MEM_MODE_SEL 0x0000000F +#define MODEM_LPCON_PWR_MEM_MODE_SEL_M ((MODEM_LPCON_PWR_MEM_MODE_SEL_V)<<(MODEM_LPCON_PWR_MEM_MODE_SEL_S)) +#define MODEM_LPCON_PWR_MEM_MODE_SEL_V 0xF +#define MODEM_LPCON_PWR_MEM_MODE_SEL_S 0 + +#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x58) +/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2508150 ; */ +/*description: .*/ +#define MODEM_LPCON_DATE 0x0FFFFFFF +#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) +#define MODEM_LPCON_DATE_V 0xFFFFFFF +#define MODEM_LPCON_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/modem/modem_lpcon_struct.h b/components/soc/esp32s31/include/modem/modem_lpcon_struct.h new file mode 100644 index 00000000000..10d0e74188d --- /dev/null +++ b/components/soc/esp32s31/include/modem/modem_lpcon_struct.h @@ -0,0 +1,287 @@ +/** + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t clk_en : 1; + uint32_t reserved1 : 1; + uint32_t reserved2 : 30; + }; + uint32_t val; + } test_conf; + union { + struct { + uint32_t clk_lp_timer_sel_osc_slow : 1; + uint32_t clk_lp_timer_sel_osc_fast : 1; + uint32_t clk_lp_timer_sel_xtal : 1; + uint32_t clk_lp_timer_sel_xtal32k : 1; + uint32_t clk_lp_timer_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } lp_timer_conf; + union { + struct { + uint32_t clk_coex_lp_sel_osc_slow : 1; + uint32_t clk_coex_lp_sel_osc_fast : 1; + uint32_t clk_coex_lp_sel_xtal : 1; + uint32_t clk_coex_lp_sel_xtal32k : 1; + uint32_t clk_coex_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } coex_lp_clk_conf; + union { + struct { + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal : 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num : 12; + uint32_t reserved16 : 16; + }; + uint32_t val; + } wifi_lp_clk_conf; + union { + struct { + uint32_t clk_modem_aon_force : 2; + uint32_t modem_pwr_clk_src_fo : 1; + uint32_t reserved3 : 29; + }; + uint32_t val; + } modem_src_clk_conf; + union { + struct { + uint32_t clk_modem_32k_sel : 2; + uint32_t reserved2 : 30; + }; + uint32_t val; + } modem_32k_clk_conf; + union { + struct { + uint32_t clk_wifipwr_en : 1; + uint32_t clk_coex_en : 1; + uint32_t clk_i2c_mst_en : 1; + uint32_t clk_lp_timer_en : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t clk_wifipwr_fo : 1; + uint32_t clk_coex_fo : 1; + uint32_t clk_i2c_mst_fo : 1; + uint32_t clk_lp_timer_fo : 1; + uint32_t clk_fe_mem_fo : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } clk_conf_force_on; + union { + struct { + uint32_t reserved0 : 16; + uint32_t clk_wifipwr_st_map : 4; + uint32_t clk_coex_st_map : 4; + uint32_t clk_i2c_mst_st_map : 4; + uint32_t clk_lp_apb_st_map : 4; + }; + uint32_t val; + } clk_conf_power_st; + union { + struct { + uint32_t rst_wifipwr : 1; + uint32_t rst_coex : 1; + uint32_t rst_i2c_mst : 1; + uint32_t rst_lp_timer : 1; + uint32_t rst_dcmem : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t reserved8 : 1; + uint32_t reserved9 : 1; + uint32_t reserved10 : 1; + uint32_t reserved11 : 1; + uint32_t reserved12 : 1; + uint32_t reserved13 : 1; + uint32_t reserved14 : 1; + uint32_t reserved15 : 1; + uint32_t reserved16 : 1; + uint32_t reserved17 : 1; + uint32_t reserved18 : 1; + uint32_t reserved19 : 1; + uint32_t reserved20 : 1; + uint32_t reserved21 : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } rst_conf; + union { + struct { + uint32_t modem_pwr_tick_target : 6; + uint32_t reserved6 : 26; + }; + uint32_t val; + } tick_conf; + union { + struct { + uint32_t dc_mem_mode : 3; + uint32_t dc_mem_force : 1; + uint32_t agc_mem_mode : 3; + uint32_t agc_mem_force : 1; + uint32_t pbus_mem_mode : 3; + uint32_t pbus_mem_force : 1; + uint32_t bc_mem_mode : 3; + uint32_t bc_mem_force : 1; + uint32_t i2c_mst_mem_mode : 3; + uint32_t i2c_mst_mem_force : 1; + uint32_t chan_freq_mem_mode : 3; + uint32_t chan_freq_mem_force : 1; + uint32_t cfr_mem_mode : 3; + uint32_t cfr_mem_force : 1; + uint32_t reserved28 : 1; + uint32_t reserved29 : 1; + uint32_t reserved30 : 1; + uint32_t reserved31 : 1; + }; + uint32_t val; + } mem_conf; + uint32_t mem_rf1_aux_ctrl; + uint32_t mem_rf2_aux_ctrl; + union { + struct { + uint32_t chan_freq_mem_en : 1; + uint32_t pbus_mem_en : 1; + uint32_t agc_mem_en : 1; + uint32_t cfr_mem_en : 1; + uint32_t pwr_mem_base : 16; + uint32_t reserved20 : 12; + }; + uint32_t val; + } apb_mem_sel; + uint32_t dcmem_valid_0; + uint32_t dcmem_valid_1; + uint32_t dcmem_valid_2; + uint32_t dcmem_valid_3; + union { + struct { + uint32_t wifi_mac_intr_wakeup_en : 1; + uint32_t wifi_mac_nmi_wakeup_en : 1; + uint32_t wifi_pwr_intr_wakeup_en : 1; + uint32_t wifi_bb_intr_wakeup_en : 1; + uint32_t bt_mac_intr_wakeup_en : 1; + uint32_t bt_bb_intr_wakeup_en : 1; + uint32_t bt_bb_nmi_wakeup_en : 1; + uint32_t lp_timer_intr_wakeup_en : 1; + uint32_t coex_intr_wakeup_en : 1; + uint32_t ble_timer_intr_wakeup_en : 1; + uint32_t ble_sec_intr_wakeup_en : 1; + uint32_t i2c_mst_intr_wakeup_en : 1; + uint32_t zb_mac_intr_wakeup_en : 1; + uint32_t bt_mac_int1_wakeup_en : 1; + uint32_t reserved14 : 18; + }; + uint32_t val; + } modem_intr_wakeup_conf; + union { + struct { + uint32_t modem_intr_vector : 14; + uint32_t reserved14 : 18; + }; + uint32_t val; + } modem_intr_status; + union { + struct { + uint32_t pwr_mem_mode_sel : 4; + uint32_t reserved4 : 28; + }; + uint32_t val; + } mem_conf2; + union { + struct { + uint32_t date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_lpcon_dev_t; +extern modem_lpcon_dev_t MODEM_LPCON; +#ifndef __cplusplus +_Static_assert(sizeof(modem_lpcon_dev_t) == 0x5c, "Invalid size of modem_lpcon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/modem/modem_syscon_reg.h b/components/soc/esp32s31/include/modem/modem_syscon_reg.h new file mode 100644 index 00000000000..0cfea21587e --- /dev/null +++ b/components/soc/esp32s31/include/modem/modem_syscon_reg.h @@ -0,0 +1,637 @@ +/** + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif +#include "reg_base.h" + +#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) +/* MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE (BIT(9)) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_M (BIT(9)) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V 0x1 +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S 9 +/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (BIT(8)) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x1 +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 +/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (BIT(7)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 +/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (BIT(6)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 +/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (BIT(5)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 +/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (BIT(4)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 +/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (BIT(3)) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x1 +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 +/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1 +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 +/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1 +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 +/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_EN (BIT(0)) +#define MODEM_SYSCON_CLK_EN_M (BIT(0)) +#define MODEM_SYSCON_CLK_EN_V 0x1 +#define MODEM_SYSCON_CLK_EN_S 0 + +#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) +/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 +/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 +/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 +/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 +/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 +/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 +/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 +/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 +/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 +/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 +#define MODEM_SYSCON_CLK_ETM_EN_S 22 +/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 +/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (BIT(12)) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x1 +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 +/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (BIT(11)) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x1 +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 +/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (BIT(10)) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x1 +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 +/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (BIT(9)) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x1 +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 +/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */ +/*description: .*/ +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FF +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S)) +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0xFF +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 +/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA (BIT(0)) +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (BIT(0)) +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x1 +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S 0 + +#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) +/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 +/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 +/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 +/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 +#define MODEM_SYSCON_CLK_ETM_FO_S 28 +/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 +/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 +/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 +/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 +/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_BTBB_FO_S 5 +/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 +/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_V 0x1 +#define MODEM_SYSCON_CLK_FE_FO_S 3 +/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 +/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_FO_S 0 + +#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) +/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)) +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 +/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)) +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 +/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S)) +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 +/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S)) +#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 +/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S)) +#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 +/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F +#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S)) +#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF +#define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 + +#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) +/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 +#define MODEM_SYSCON_RST_DATA_DUMP_S 31 +/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 +#define MODEM_SYSCON_RST_BLE_TIMER_S 30 +/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 +#define MODEM_SYSCON_RST_MODEM_SEC_S 29 +/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 +#define MODEM_SYSCON_RST_MODEM_BAH_S 27 +/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 +#define MODEM_SYSCON_RST_MODEM_CCM_S 26 +/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 +#define MODEM_SYSCON_RST_MODEM_ECB_S 25 +/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_V 0x1 +#define MODEM_SYSCON_RST_ZBMAC_S 24 +/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) +#define MODEM_SYSCON_RST_ZBMAC_APB_M (BIT(23)) +#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x1 +#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 +/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_ETM (BIT(22)) +#define MODEM_SYSCON_RST_ETM_M (BIT(22)) +#define MODEM_SYSCON_RST_ETM_V 0x1 +#define MODEM_SYSCON_RST_ETM_S 22 +/* MODEM_SYSCON_RST_COEX_BTMAC : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_COEX_BTMAC (BIT(20)) +#define MODEM_SYSCON_RST_COEX_BTMAC_M (BIT(20)) +#define MODEM_SYSCON_RST_COEX_BTMAC_V 0x1 +#define MODEM_SYSCON_RST_COEX_BTMAC_S 20 +/* MODEM_SYSCON_RST_COEX_BTMAC_APB : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_COEX_BTMAC_APB (BIT(19)) +#define MODEM_SYSCON_RST_COEX_BTMAC_APB_M (BIT(19)) +#define MODEM_SYSCON_RST_COEX_BTMAC_APB_V 0x1 +#define MODEM_SYSCON_RST_COEX_BTMAC_APB_S 19 +/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTBB (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_V 0x1 +#define MODEM_SYSCON_RST_BTBB_S 18 +/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 +#define MODEM_SYSCON_RST_BTBB_APB_S 17 +/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTMAC (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_V 0x1 +#define MODEM_SYSCON_RST_BTMAC_S 16 +/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 +#define MODEM_SYSCON_RST_BTMAC_APB_S 15 +/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE (BIT(14)) +#define MODEM_SYSCON_RST_FE_M (BIT(14)) +#define MODEM_SYSCON_RST_FE_V 0x1 +#define MODEM_SYSCON_RST_FE_S 14 +/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_V 0x1 +#define MODEM_SYSCON_RST_FE_AHB_S 13 +/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_V 0x1 +#define MODEM_SYSCON_RST_FE_ADC_S 12 +/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_V 0x1 +#define MODEM_SYSCON_RST_FE_DAC_S 11 +/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1 +#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 +/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_V 0x1 +#define MODEM_SYSCON_RST_WIFIMAC_S 9 +/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_RST_WIFIBB (BIT(8)) +#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8)) +#define MODEM_SYSCON_RST_WIFIBB_V 0x1 +#define MODEM_SYSCON_RST_WIFIBB_S 8 + +#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) +/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 +/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 +/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 +/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 +/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1 +#define MODEM_SYSCON_CLK_BTBB_EN_S 17 +/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 +/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 +/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 +/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 +/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 +/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 +/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 +/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 +/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 +/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 +/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 +/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 +/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 +/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 +/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 +/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 +/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0)) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 + +#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) +/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF +#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S)) +#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +#define MODEM_SYSCON_WIFI_BB_CFG_S 0 + +#define MODEM_SYSCON_FE_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) +/* MODEM_SYSCON_FE_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_FE_CFG 0xFFFFFFFF +#define MODEM_SYSCON_FE_CFG_M ((MODEM_SYSCON_FE_CFG_V)<<(MODEM_SYSCON_FE_CFG_S)) +#define MODEM_SYSCON_FE_CFG_V 0xFFFFFFFF +#define MODEM_SYSCON_FE_CFG_S 0 + +#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) +/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)) +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0 + +#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) +/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)) +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0 + +#define MODEM_SYSCON_BTMAC_CLK_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x28) +/* MODEM_SYSCON_CLK_BTMAC_LOW_RATE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: .*/ +#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE (BIT(0)) +#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE_M (BIT(0)) +#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE_V 0x1 +#define MODEM_SYSCON_CLK_BTMAC_LOW_RATE_S 0 + +#define MODEM_SYSCON_MEM_MODE_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x2C) +/* MODEM_SYSCON_MODEM_RF2_MEM_SEL : R/W ;bitpos:[7:4] ;default: 4'b0100 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF2_MEM_SEL 0x0000000F +#define MODEM_SYSCON_MODEM_RF2_MEM_SEL_M ((MODEM_SYSCON_MODEM_RF2_MEM_SEL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_SEL_S)) +#define MODEM_SYSCON_MODEM_RF2_MEM_SEL_V 0xF +#define MODEM_SYSCON_MODEM_RF2_MEM_SEL_S 4 +/* MODEM_SYSCON_MODEM_RF1_MEM_SEL : R/W ;bitpos:[3:0] ;default: 4'b0100 ; */ +/*description: .*/ +#define MODEM_SYSCON_MODEM_RF1_MEM_SEL 0x0000000F +#define MODEM_SYSCON_MODEM_RF1_MEM_SEL_M ((MODEM_SYSCON_MODEM_RF1_MEM_SEL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_SEL_S)) +#define MODEM_SYSCON_MODEM_RF1_MEM_SEL_V 0xF +#define MODEM_SYSCON_MODEM_RF1_MEM_SEL_S 0 + +#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x30) +/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2508080 ; */ +/*description: .*/ +#define MODEM_SYSCON_DATE 0x0FFFFFFF +#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) +#define MODEM_SYSCON_DATE_V 0xFFFFFFF +#define MODEM_SYSCON_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/modem/modem_syscon_struct.h b/components/soc/esp32s31/include/modem/modem_syscon_struct.h new file mode 100644 index 00000000000..584eb7f7cf0 --- /dev/null +++ b/components/soc/esp32s31/include/modem/modem_syscon_struct.h @@ -0,0 +1,192 @@ +/** + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t clk_en : 1; + uint32_t modem_ant_force_sel_bt : 1; + uint32_t modem_ant_force_sel_wifi : 1; + uint32_t fpga_debug_clkswitch : 1; + uint32_t fpga_debug_clk80 : 1; + uint32_t fpga_debug_clk40 : 1; + uint32_t fpga_debug_clk20 : 1; + uint32_t fpga_debug_clk10 : 1; + uint32_t modem_mem_mode_force : 1; + uint32_t modem_dis_wifi6_force : 1; + uint32_t reserved10 : 22; + }; + uint32_t val; + } test_conf; + union { + struct { + uint32_t pwdet_sar_clock_ena : 1; + uint32_t pwdet_clk_div_num : 8; + uint32_t clk_tx_dac_inv_ena : 1; + uint32_t clk_rx_adc_inv_ena : 1; + uint32_t clk_pwdet_adc_inv_ena : 1; + uint32_t clk_i2c_mst_sel_160m : 1; + uint32_t reserved13 : 8; + uint32_t clk_data_dump_mux : 1; + uint32_t clk_etm_en : 1; + uint32_t clk_zb_apb_en : 1; + uint32_t clk_zbmac_en : 1; + uint32_t clk_modem_sec_ecb_en : 1; + uint32_t clk_modem_sec_ccm_en : 1; + uint32_t clk_modem_sec_bah_en : 1; + uint32_t clk_modem_sec_apb_en : 1; + uint32_t clk_modem_sec_en : 1; + uint32_t clk_ble_timer_en : 1; + uint32_t clk_data_dump_en : 1; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t clk_wifibb_fo : 1; + uint32_t clk_wifimac_fo : 1; + uint32_t clk_wifi_apb_fo : 1; + uint32_t clk_fe_fo : 1; + uint32_t clk_fe_apb_fo : 1; + uint32_t clk_btbb_fo : 1; + uint32_t clk_btmac_fo : 1; + uint32_t clk_bt_apb_fo : 1; + uint32_t clk_zbmac_fo : 1; + uint32_t clk_zbmac_apb_fo : 1; + uint32_t reserved10 : 13; + uint32_t reserved23 : 1; + uint32_t reserved24 : 1; + uint32_t reserved25 : 1; + uint32_t reserved26 : 1; + uint32_t reserved27 : 1; + uint32_t clk_etm_fo : 1; + uint32_t clk_modem_sec_fo : 1; + uint32_t clk_ble_timer_fo : 1; + uint32_t clk_data_dump_fo : 1; + }; + uint32_t val; + } clk_conf_force_on; + union { + struct { + uint32_t reserved0 : 8; + uint32_t clk_zb_st_map : 4; + uint32_t clk_fe_st_map : 4; + uint32_t clk_bt_st_map : 4; + uint32_t clk_wifi_st_map : 4; + uint32_t clk_modem_peri_st_map : 4; + uint32_t clk_modem_apb_st_map : 4; + }; + uint32_t val; + } clk_conf_power_st; + union { + struct { + uint32_t reserved0 : 1; + uint32_t reserved1 : 1; + uint32_t reserved2 : 1; + uint32_t reserved3 : 1; + uint32_t reserved4 : 1; + uint32_t reserved5 : 1; + uint32_t reserved6 : 1; + uint32_t reserved7 : 1; + uint32_t rst_wifibb : 1; + uint32_t rst_wifimac : 1; + uint32_t rst_fe_pwdet_adc : 1; + uint32_t rst_fe_dac : 1; + uint32_t rst_fe_adc : 1; + uint32_t rst_fe_ahb : 1; + uint32_t rst_fe : 1; + uint32_t rst_btmac_apb : 1; + uint32_t rst_btmac : 1; + uint32_t rst_btbb_apb : 1; + uint32_t rst_btbb : 1; + uint32_t rst_coex_btmac_apb : 1; + uint32_t rst_coex_btmac : 1; + uint32_t reserved21 : 1; + uint32_t rst_etm : 1; + uint32_t rst_zbmac_apb : 1; + uint32_t rst_zbmac : 1; + uint32_t rst_modem_ecb : 1; + uint32_t rst_modem_ccm : 1; + uint32_t rst_modem_bah : 1; + uint32_t reserved28 : 1; + uint32_t rst_modem_sec : 1; + uint32_t rst_ble_timer : 1; + uint32_t rst_data_dump : 1; + }; + uint32_t val; + } modem_rst_conf; + union { + struct { + uint32_t clk_wifibb_22m_en : 1; + uint32_t clk_wifibb_40m_en : 1; + uint32_t clk_wifibb_44m_en : 1; + uint32_t clk_wifibb_80m_en : 1; + uint32_t clk_wifibb_40x_en : 1; + uint32_t clk_wifibb_80x_en : 1; + uint32_t clk_wifibb_40x1_en : 1; + uint32_t clk_wifibb_80x1_en : 1; + uint32_t clk_wifibb_160x1_en : 1; + uint32_t clk_wifimac_en : 1; + uint32_t clk_wifi_apb_en : 1; + uint32_t clk_fe_20m_en : 1; + uint32_t clk_fe_40m_en : 1; + uint32_t clk_fe_80m_en : 1; + uint32_t clk_fe_160m_en : 1; + uint32_t clk_fe_apb_en : 1; + uint32_t clk_bt_apb_en : 1; + uint32_t clk_btbb_en : 1; + uint32_t clk_btmac_en : 1; + uint32_t clk_fe_pwdet_adc_en : 1; + uint32_t clk_fe_adc_en : 1; + uint32_t clk_fe_dac_en : 1; + uint32_t reserved22 : 1; + uint32_t reserved23 : 1; + uint32_t reserved24 : 8; + }; + uint32_t val; + } clk_conf1; + uint32_t wifi_bb_cfg; + uint32_t fe_cfg; + uint32_t mem_rf1_conf; + uint32_t mem_rf2_conf; + union { + struct { + uint32_t clk_btmac_low_rate : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; + } btmac_clk_cfg; + union { + struct { + uint32_t modem_rf1_mem_sel : 4; + uint32_t modem_rf2_mem_sel : 4; + uint32_t reserved8 : 24; + }; + uint32_t val; + } mem_mode_conf; + union { + struct { + uint32_t date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_syscon_dev_t; +extern modem_syscon_dev_t MODEM_SYSCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_syscon_dev_t) == 0x34, "Invalid size of modem_syscon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/modem/modem_widgets_reg.h b/components/soc/esp32s31/include/modem/modem_widgets_reg.h new file mode 100644 index 00000000000..2cb66ed237b --- /dev/null +++ b/components/soc/esp32s31/include/modem/modem_widgets_reg.h @@ -0,0 +1,79 @@ +/** + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif +#include "reg_base.h" + +#define MODEM_WIDGETS_CLK_CONF_REG (DR_REG_MODEM_WIDGETS_BASE + 0x0) +/* MODEM_WIDGETS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_CLK_EN (BIT(0)) +#define MODEM_WIDGETS_CLK_EN_M (BIT(0)) +#define MODEM_WIDGETS_CLK_EN_V 0x1 +#define MODEM_WIDGETS_CLK_EN_S 0 + +#define MODEM_WIDGETS_MODEM_DIAG_FIX_SEL_REG (DR_REG_MODEM_WIDGETS_BASE + 0x4) +/* MODEM_WIDGETS_DIAG_BUS_FIX_LOW_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DIAG_BUS_FIX_LOW_EN (BIT(10)) +#define MODEM_WIDGETS_DIAG_BUS_FIX_LOW_EN_M (BIT(10)) +#define MODEM_WIDGETS_DIAG_BUS_FIX_LOW_EN_V 0x1 +#define MODEM_WIDGETS_DIAG_BUS_FIX_LOW_EN_S 10 +/* MODEM_WIDGETS_DIAG_BUS_FIX_SEL_LOW : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_LOW 0x0000001F +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_LOW_M ((MODEM_WIDGETS_DIAG_BUS_FIX_SEL_LOW_V)<<(MODEM_WIDGETS_DIAG_BUS_FIX_SEL_LOW_S)) +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_LOW_V 0x1F +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_LOW_S 5 +/* MODEM_WIDGETS_DIAG_BUS_FIX_SEL_HIGH : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_HIGH 0x0000001F +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_HIGH_M ((MODEM_WIDGETS_DIAG_BUS_FIX_SEL_HIGH_V)<<(MODEM_WIDGETS_DIAG_BUS_FIX_SEL_HIGH_S)) +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_HIGH_V 0x1F +#define MODEM_WIDGETS_DIAG_BUS_FIX_SEL_HIGH_S 0 + +#define MODEM_WIDGETS_MODEM_DIAG_EXCHANGE_REG (DR_REG_MODEM_WIDGETS_BASE + 0x8) +/* MODEM_WIDGETS_DIAG_BUS_EXCHANGE3_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE3_SEL 0x0000000F +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE3_SEL_M ((MODEM_WIDGETS_DIAG_BUS_EXCHANGE3_SEL_V)<<(MODEM_WIDGETS_DIAG_BUS_EXCHANGE3_SEL_S)) +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE3_SEL_V 0xF +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE3_SEL_S 12 +/* MODEM_WIDGETS_DIAG_BUS_EXCHANGE2_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE2_SEL 0x0000000F +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE2_SEL_M ((MODEM_WIDGETS_DIAG_BUS_EXCHANGE2_SEL_V)<<(MODEM_WIDGETS_DIAG_BUS_EXCHANGE2_SEL_S)) +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE2_SEL_V 0xF +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE2_SEL_S 8 +/* MODEM_WIDGETS_DIAG_BUS_EXCHANGE1_SEL : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE1_SEL 0x0000000F +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE1_SEL_M ((MODEM_WIDGETS_DIAG_BUS_EXCHANGE1_SEL_V)<<(MODEM_WIDGETS_DIAG_BUS_EXCHANGE1_SEL_S)) +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE1_SEL_V 0xF +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE1_SEL_S 4 +/* MODEM_WIDGETS_DIAG_BUS_EXCHANGE0_SEL : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE0_SEL 0x0000000F +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE0_SEL_M ((MODEM_WIDGETS_DIAG_BUS_EXCHANGE0_SEL_V)<<(MODEM_WIDGETS_DIAG_BUS_EXCHANGE0_SEL_S)) +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE0_SEL_V 0xF +#define MODEM_WIDGETS_DIAG_BUS_EXCHANGE0_SEL_S 0 + +#define MODEM_WIDGETS_DATE_REG (DR_REG_MODEM_WIDGETS_BASE + 0xC) +/* MODEM_WIDGETS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202221 ; */ +/*description: .*/ +#define MODEM_WIDGETS_DATE 0x0FFFFFFF +#define MODEM_WIDGETS_DATE_M ((MODEM_WIDGETS_DATE_V)<<(MODEM_WIDGETS_DATE_S)) +#define MODEM_WIDGETS_DATE_V 0xFFFFFFF +#define MODEM_WIDGETS_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/modem/modem_widgets_struct.h b/components/soc/esp32s31/include/modem/modem_widgets_struct.h new file mode 100644 index 00000000000..680286eafd5 --- /dev/null +++ b/components/soc/esp32s31/include/modem/modem_widgets_struct.h @@ -0,0 +1,56 @@ +/** + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef volatile struct { + union { + struct { + uint32_t reg_clk_en : 1; + uint32_t reserved1 : 31; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reg_diag_bus_fix_sel_high : 5; + uint32_t reg_diag_bus_fix_sel_low : 5; + uint32_t reg_diag_bus_fix_low_en : 1; + uint32_t reserved11 : 21; + }; + uint32_t val; + } modem_diag_fix_sel; + union { + struct { + uint32_t reg_diag_bus_exchange0_sel : 4; + uint32_t reg_diag_bus_exchange1_sel : 4; + uint32_t reg_diag_bus_exchange2_sel : 4; + uint32_t reg_diag_bus_exchange3_sel : 4; + uint32_t reserved16 : 16; + }; + uint32_t val; + } modem_diag_exchange; + union { + struct { + uint32_t reg_date : 28; + uint32_t reserved28 : 4; + }; + uint32_t val; + } date; +} modem_widgets_dev_t; +extern modem_widgets_dev_t MODEM_WIDGETS; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_widgets_dev_t) == 0x10, "Invalid size of modem_widgets_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/modem/reg_base.h b/components/soc/esp32s31/include/modem/reg_base.h new file mode 100644 index 00000000000..4df4112b03c --- /dev/null +++ b/components/soc/esp32s31/include/modem/reg_base.h @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +#define MODEM_BASE 0x20100000 +#define MODEM_PWR_BASE 0x2010D000 + +#define DR_REG_FE_BASE (MODEM_BASE + 0x0000) +#define DR_REG_WIFI_MAC_BASE (MODEM_BASE + 0x4000) +#define DR_REG_WIFI_BB_BASE (MODEM_BASE + 0x7000) +#define DR_REG_WIFI_BB_BRX_BASE (MODEM_BASE + 0x8000) +#define DR_REG_MODEM_TIMER_BASE (MODEM_BASE + 0x8400) +#define DR_REG_MODEM_ETM_BASE (MODEM_BASE + 0x8800) +#define DR_REG_MODEM_DATADUMP_BASE (MODEM_BASE + 0x9000) +#define DR_REG_MODEM_WIDGETS_BASE (MODEM_BASE + 0x9400) +#define DR_REG_MODEM_SYSCON_BASE (MODEM_BASE + 0x9C00) + +#define DR_REG_MODEM_LPCON_BASE (MODEM_PWR_BASE + 0x2000) diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 86f0e3b2371..9ce4168e5e1 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -51,6 +51,10 @@ config SOC_SYSTIMER_SUPPORTED bool default y +config SOC_PAU_SUPPORTED + bool + default y + config SOC_PMU_SUPPORTED bool default y @@ -191,10 +195,6 @@ config SOC_GDMA_SUPPORT_ETM bool default y -config SOC_GDMA_SUPPORT_SLEEP_RETENTION - bool - default y - config SOC_GDMA_EXT_MEM_ENC_ALIGNMENT int default 16 @@ -307,18 +307,10 @@ config SOC_TIMER_SUPPORT_ETM bool default y -config SOC_TIMER_SUPPORT_SLEEP_RETENTION - bool - default y - config SOC_MWDT_SUPPORT_XTAL bool default y -config SOC_MWDT_SUPPORT_SLEEP_RETENTION - bool - default y - config SOC_EFUSE_DIS_PAD_JTAG bool default y @@ -467,10 +459,6 @@ config SOC_PM_SUPPORT_VDDSDIO_PD bool default y -config SOC_PM_SUPPORT_TOP_PD - bool - default y - config SOC_PM_SUPPORT_HP_AON_PD bool default y diff --git a/components/soc/esp32s31/include/soc/retention_periph_defs.h b/components/soc/esp32s31/include/soc/retention_periph_defs.h new file mode 100644 index 00000000000..ff690a6d962 --- /dev/null +++ b/components/soc/esp32s31/include/soc/retention_periph_defs.h @@ -0,0 +1,84 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ + +#pragma once + +#include +#include "soc_caps.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum periph_retention_module { + SLEEP_RETENTION_MODULE_MIN = 0, + SLEEP_RETENTION_MODULE_NULL = 1, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */ + /* clock module, which includes system and modem */ + SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 2, + /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM, + * TEE, APM, UART, IOMUX, SPIMEM, SysTimer, etc.. */ + SLEEP_RETENTION_MODULE_SYS_PERIPH = 3, + /* Timer Group by target*/ + SLEEP_RETENTION_MODULE_TG0_WDT = 4, + SLEEP_RETENTION_MODULE_TG1_WDT = 5, + SLEEP_RETENTION_MODULE_TG0_TIMER0 = 6, + SLEEP_RETENTION_MODULE_TG0_TIMER1 = 7, + SLEEP_RETENTION_MODULE_TG1_TIMER0 = 8, + SLEEP_RETENTION_MODULE_TG1_TIMER1 = 9, + + /* AHB_DMA by channel */ + SLEEP_RETENTION_MODULE_AHB_DMA_CH0 = 10, + SLEEP_RETENTION_MODULE_AHB_DMA_CH1 = 11, + SLEEP_RETENTION_MODULE_AHB_DMA_CH2 = 12, + SLEEP_RETENTION_MODULE_AHB_DMA_CH3 = 13, + SLEEP_RETENTION_MODULE_AHB_DMA_CH4 = 14, + /* AXI_DMA by channel */ + SLEEP_RETENTION_MODULE_AXI_DMA_CH0 = 15, + SLEEP_RETENTION_MODULE_AXI_DMA_CH1 = 16, + SLEEP_RETENTION_MODULE_AXI_DMA_CH2 = 17, + /* MISC Peripherals */ + SLEEP_RETENTION_MODULE_UART0 = 18, + SLEEP_RETENTION_MODULE_UART1 = 19, + SLEEP_RETENTION_MODULE_UART2 = 20, + SLEEP_RETENTION_MODULE_UART3 = 21, + SLEEP_RETENTION_MODULE_RMT0 = 22, + SLEEP_RETENTION_MODULE_I2S0 = 23, + SLEEP_RETENTION_MODULE_I2S1 = 24, + SLEEP_RETENTION_MODULE_I2C0 = 25, + SLEEP_RETENTION_MODULE_I2C1 = 26, + SLEEP_RETENTION_MODULE_ETM0 = 27, + SLEEP_RETENTION_MODULE_TWAI0 = 28, + SLEEP_RETENTION_MODULE_TWAI1 = 29, + SLEEP_RETENTION_MODULE_PARLIO0 = 30, + SLEEP_RETENTION_MODULE_GPSPI2 = 31, + SLEEP_RETENTION_MODULE_GPSPI3 = 32, + SLEEP_RETENTION_MODULE_LEDC0 = 33, + SLEEP_RETENTION_MODULE_LEDC1 = 34, + SLEEP_RETENTION_MODULE_MCPWM0 = 35, + SLEEP_RETENTION_MODULE_MCPWM1 = 36, + SLEEP_RETENTION_MODULE_MCPWM2 = 37, + SLEEP_RETENTION_MODULE_MCPWM3 = 38, + SLEEP_RETENTION_MODULE_PCNT0 = 39, + SLEEP_RETENTION_MODULE_PCNT1 = 40, + SLEEP_RETENTION_MODULE_SDM0 = 41, + + /* Modem module, which includes WiFi, BLE and 802.15.4 */ + SLEEP_RETENTION_MODULE_WIFI_MAC = 42, + SLEEP_RETENTION_MODULE_WIFI_BB = 43, + SLEEP_RETENTION_MODULE_BLE_MAC = 44, + SLEEP_RETENTION_MODULE_BT_BB = 45, + SLEEP_RETENTION_MODULE_802154_MAC = 46, + SLEEP_RETENTION_MODULE_CLOCK_MODEM = 47, + SLEEP_RETENTION_MODULE_MODEM_PHY = 48, + + SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1 +} periph_retention_module_t; + +#define is_top_domain_module(m) ((m >= SLEEP_RETENTION_MODULE_CLOCK_SYSTEM) && ((m <= SLEEP_RETENTION_MODULE_SDM0))) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index 3abb6f3db8e..de70ef109b8 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -72,7 +72,7 @@ // #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32S31] IDF-14629 // #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14658 // #define SOC_APM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14620 -// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32S31] IDF-14582 +#define SOC_PAU_SUPPORTED 1 #define SOC_PMU_SUPPORTED 1 #define SOC_RTC_TIMER_SUPPORTED 1 // #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14634 @@ -146,7 +146,7 @@ /*-------------------------- GDMA CAPS -------------------------------------*/ #define SOC_AHB_GDMA_VERSION 2 #define SOC_GDMA_SUPPORT_ETM 1 -#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 +// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: [ESP32S31] IDF-14760 #define SOC_GDMA_EXT_MEM_ENC_ALIGNMENT (16) /*-------------------------- APM CAPS ----------------------------------------*/ @@ -228,11 +228,11 @@ /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_SUPPORT_ETM (1) -#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) +// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) // TODO: [ESP32S31] IDF-14746 /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ #define SOC_MWDT_SUPPORT_XTAL (1) -#define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) +// #define SOC_MWDT_SUPPORT_SLEEP_RETENTION (1) /*-------------------------- eFuse CAPS----------------------------*/ // TODO: [ESP32S31] IDF-14688 @@ -299,7 +299,7 @@ #define SOC_PM_SUPPORT_RC32K_PD (1) #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) -#define SOC_PM_SUPPORT_TOP_PD (1) +// #define SOC_PM_SUPPORT_TOP_PD (1) // TODO: [ESP32S31] IDF-14647 #define SOC_PM_SUPPORT_HP_AON_PD (1) #define SOC_PM_SUPPORT_CNNT_PD (1) #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) diff --git a/components/soc/esp32s31/include/soc/system_periph_retention.h b/components/soc/esp32s31/include/soc/system_periph_retention.h index 6680539a7c3..7fa9390cd7e 100644 --- a/components/soc/esp32s31/include/soc/system_periph_retention.h +++ b/components/soc/esp32s31/include/soc/system_periph_retention.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -23,17 +23,17 @@ extern "C" * useful for external use. */ #define INT_MTX_RETENTION_LINK_LEN 2 -// extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN]; +extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN]; /** - * @brief Provide access to cache configuration registers retention + * @brief Provide access to tee apm configuration registers retention * context definition. * * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define CACHE_RETENTION_LINK_LEN 8 -// extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN]; +#define TEE_APM_RETENTION_LINK_LEN 14 +extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN]; /** * @brief Provide access to hp_system configuration registers retention @@ -43,7 +43,7 @@ extern "C" * useful for external use. */ #define HP_SYSTEM_RETENTION_LINK_LEN 1 -// extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN]; +extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN]; /** * @brief Provide access to IOMUX configuration registers retention @@ -52,8 +52,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define IOMUX_RETENTION_LINK_LEN 6 -// extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN]; +#define IOMUX_RETENTION_LINK_LEN 5 +extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN]; /** * @brief Provide access to FLASH spimem configuration registers retention @@ -62,8 +62,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define SPIMEM_FLASH_RETENTION_LINK_LEN 8 -// extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_FLASH_RETENTION_LINK_LEN]; +#define SPIMEM_FLASH_RETENTION_LINK_LEN 7 +extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_FLASH_RETENTION_LINK_LEN]; /** * @brief Provide access to PSRAM spimem configuration registers retention @@ -72,8 +72,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define SPIMEM_PSRAM_RETENTION_LINK_LEN 14 -// extern const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN]; +#define SPIMEM_PSRAM_RETENTION_LINK_LEN 5 +extern const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN]; /** * @brief Provide access to systimer configuration registers retention @@ -82,8 +82,8 @@ extern "C" * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define SYSTIMER_RETENTION_LINK_LEN 19 -// extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN]; +#define SYSTIMER_RETENTION_LINK_LEN 10 +extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN]; /** * @brief Provide access to pau configuration registers retention @@ -93,7 +93,7 @@ extern "C" * useful for external use. */ #define PAU_RETENTION_LINK_LEN 1 -// extern const regdma_entries_config_t pau_regs_retention[PAU_RETENTION_LINK_LEN]; +extern const regdma_entries_config_t pau_regs_retention[PAU_RETENTION_LINK_LEN]; #ifdef __cplusplus } diff --git a/components/soc/esp32s31/ld/esp32s31.peripherals.ld b/components/soc/esp32s31/ld/esp32s31.peripherals.ld index 61df5446b5e..e47f458664d 100644 --- a/components/soc/esp32s31/ld/esp32s31.peripherals.ld +++ b/components/soc/esp32s31/ld/esp32s31.peripherals.ld @@ -77,7 +77,7 @@ PROVIDE ( MSPI_IOMUX = 0x20584000 ); PROVIDE ( HP_SYSTEM = 0x20586000 ); PROVIDE ( HP_SYS_CLKRST = 0x20587000 ); PROVIDE ( CNNT_PAD_CTRL = 0x20588000 ); -PROVIDE ( HP_ALIVE_SYS_REG = 0x20589000 ); +PROVIDE ( HP_ALIVE_SYS = 0x20589000 ); PROVIDE ( HP_PERI1_PMS = 0x2058A000 ); PROVIDE ( LP_SYS = 0x20700000 ); PROVIDE ( LP_CLKRST = 0x20701000 ); diff --git a/components/soc/esp32s31/register/soc/reg_base.h b/components/soc/esp32s31/register/soc/reg_base.h index 97f8473038c..609b3478847 100644 --- a/components/soc/esp32s31/register/soc/reg_base.h +++ b/components/soc/esp32s31/register/soc/reg_base.h @@ -73,7 +73,7 @@ #define DR_REG_IO_MUX_BASE 0x20582000 #define DR_REG_GPIO_BASE 0x20583000 #define DR_REG_GPIO_EXT_BASE 0x20583E00 -#define DR_REG_MSPI_IOMUX_BASE 0x20584000 +#define DR_REG_IOMUX_MSPI_PIN_BASE 0x20584000 #define DR_REG_INTR0_BASE 0x20585000 #define DR_REG_HP_SYS_BASE 0x20586000 #define DR_REG_HP_SYS_CLKRST_BASE 0x20587000 diff --git a/components/soc/esp32s31/system_retention_periph.c b/components/soc/esp32s31/system_retention_periph.c new file mode 100644 index 00000000000..56b461576a8 --- /dev/null +++ b/components/soc/esp32s31/system_retention_periph.c @@ -0,0 +1,164 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 OR MIT + */ +#include "soc/cache_reg.h" +#include "soc/gpio_reg.h" +#include "soc/hp_system_reg.h" +#include "soc/hp_sys_clkrst_reg.h" +#include "soc/io_mux_reg.h" +#include "soc/iomux_mspi_pin_reg.h" +#include "soc/interrupt_core0_reg.h" +#include "soc/interrupt_core1_reg.h" +#include "soc/pau_reg.h" +#include "soc/regdma.h" +#include "soc/system_periph_retention.h" +#include "soc/spi_mem_reg.h" +#include "soc/spi_mem_s_reg.h" +#include "soc/spi1_mem_s_reg.h" +#include "soc/systimer_reg.h" +#include "soc/timer_group_reg.h" +// #include "soc/timer_periph.h" +#include "soc/uart_reg.h" +#include "esp32s31/rom/cache.h" +#include "soc/hp_apm_reg.h" +#include "soc/cpu_apm_reg.h" +#include "soc/hp_mem_apm_reg.h" +#include "soc/tee_reg.h" +#include "soc/hp_peri0_pms_reg.h" +#include "soc/hp_peri1_pms_reg.h" + +/* Interrupt Matrix Registers Context */ +#define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1) +#define N_REGS_INTR_CORE1() (((INTERRUPT_CORE1_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE1_BASE) / 4) + 1) +const regdma_entries_config_t intr_matrix_regs_retention[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x00), DR_REG_INTERRUPT_CORE0_BASE, DR_REG_INTERRUPT_CORE0_BASE, N_REGS_INTR_CORE0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* intr matrix */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x01), DR_REG_INTERRUPT_CORE1_BASE, DR_REG_INTERRUPT_CORE1_BASE, N_REGS_INTR_CORE1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */ +}; +_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions"); + +#if SOC_APM_SUPPORTED +/* TEE APM Registers Context */ +#define N_REGS_TEE_0() (((TEE_M87_MODE_CTRL_REG - TEE_M0_MODE_CTRL_REG) / 4) + 1) +#define N_REGS_TEE_1() (((TEE_SUPERVISOR_PRIV_SEL_REG - TEE_SUPERVISOR_PRIV_SEL_REG) / 4) + 1) +#define N_REGS_APM_0() (((HP_APM_FUNC_CTRL_REG - HP_APM_REGION_FILTER_EN_REG) / 4) + 1) +#define N_REGS_APM_1() (((HP_APM_BUS_ERR_CONF_REG - HP_APM_INT_EN_REG) / 4) + 1) +#define N_REGS_APM_2() (((CPU_APM_FUNC_CTRL_REG - CPU_APM_REGION_FILTER_EN_REG) / 4) + 1) +#define N_REGS_APM_3() (((CPU_APM_BUS_ERR_CONF_REG - CPU_APM_INT_EN_REG) / 4) + 1) +#define N_REGS_APM_4() (((HP_MEM_APM_FUNC_CTRL_REG - HP_MEM_APM_REGION_FILTER_EN_REG) / 4) + 1) +#define N_REGS_APM_5() (((HP_MEM_APM_BUS_ERR_CONF_REG - HP_MEM_APM_INT_EN_REG) / 4) + 1) + +#define N_REGS_PMS0_0() (((HP_PERI0_PMS_AXI_PERF_MON_CTRL_REG - HP_PERI0_PMS_TRACE0_CTRL_REG) / 4) + 1) +#define N_REGS_PMS0_1() (((HP_PERI0_PMS_INT_EN_REG - HP_PERI0_PMS_INT_EN_REG) / 4) + 1) +#define N_REGS_PMS0_2() (((HP_PERI0_PMS_CLOCK_GATE_REG - HP_PERI0_PMS_BUS_ERR_CONF_REG) / 4) + 1) +#define N_REGS_PMS1_0() (((HP_PERI1_PMS_HP_PERI1_PMS_CTRL_REG - HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG) / 4) + 1) +#define N_REGS_PMS1_1() (((HP_PERI1_PMS_INT_EN_REG - HP_PERI1_PMS_INT_EN_REG) / 4) + 1) +#define N_REGS_PMS1_2() (((HP_PERI1_PMS_CLOCK_GATE_REG - HP_PERI1_PMS_BUS_ERR_CONF_REG) / 4) + 1) + +const regdma_entries_config_t tee_apm_regs_retention[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x00), TEE_M0_MODE_CTRL_REG, TEE_M0_MODE_CTRL_REG, N_REGS_TEE_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* tee */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x01), TEE_SUPERVISOR_PRIV_SEL_REG, TEE_SUPERVISOR_PRIV_SEL_REG, N_REGS_TEE_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x02), HP_APM_REGION_FILTER_EN_REG, HP_APM_REGION_FILTER_EN_REG, N_REGS_APM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x03), HP_APM_INT_EN_REG, HP_APM_INT_EN_REG, N_REGS_APM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x04), CPU_APM_REGION_FILTER_EN_REG, CPU_APM_REGION_FILTER_EN_REG, N_REGS_APM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x05), CPU_APM_INT_EN_REG, CPU_APM_INT_EN_REG, N_REGS_APM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x06), HP_MEM_APM_REGION_FILTER_EN_REG, HP_MEM_APM_REGION_FILTER_EN_REG, N_REGS_APM_4(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x07), HP_MEM_APM_INT_EN_REG, HP_MEM_APM_INT_EN_REG, N_REGS_APM_5(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x08), HP_PERI0_PMS_TRACE0_CTRL_REG, HP_PERI0_PMS_TRACE0_CTRL_REG, N_REGS_PMS0_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [9] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x09), HP_PERI0_PMS_INT_EN_REG, HP_PERI0_PMS_INT_EN_REG, N_REGS_PMS0_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [10] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0a), HP_PERI0_PMS_BUS_ERR_CONF_REG, HP_PERI0_PMS_BUS_ERR_CONF_REG, N_REGS_PMS0_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [11] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0b), HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG, HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG, N_REGS_PMS1_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [12] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0c), HP_PERI1_PMS_INT_EN_REG, HP_PERI1_PMS_INT_EN_REG, N_REGS_PMS1_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [13] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0d), HP_PERI1_PMS_BUS_ERR_CONF_REG, HP_PERI1_PMS_BUS_ERR_CONF_REG, N_REGS_PMS1_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; +_Static_assert(ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions"); +#endif + +/* HP System Registers Context */ +#define N_REGS_HP_SYSTEM() (((HP_SYSTEM_GMAC1_PAD_BIST_INT_ENA_REG - DR_REG_HP_SYS_BASE) / 4) + 1) +const regdma_entries_config_t hp_system_regs_retention[] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_HPSYS_LINK(0), DR_REG_HP_SYS_BASE, DR_REG_HP_SYS_BASE, N_REGS_HP_SYSTEM(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* hp system */ +}; +_Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions"); + +/* IO MUX Registers Context */ +#define N_REGS_IOMUX() (((IO_MUX_GPIO62_REG - REG_IO_MUX_BASE) / 4) + 1) +#define N_REGS_MSPI_IOMUX() (((IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG - IOMUX_MSPI_PIN_CLK_EN0_REG) / 4) + 1) +#define N_REGS_GPIO_PINx() (((GPIO_PIN62_REG - GPIO_PIN0_REG) / 4) + 1) +#define N_REGS_GPIO_FUNC_IN() (((GPIO_FUNC255_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1) +#define N_REGS_GPIO_FUNC_OUT() (((GPIO_FUNC62_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1) + +const regdma_entries_config_t iomux_regs_retention[] = { + /* IO_MUX */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + /* MSPI IOMUX */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG, IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG, N_REGS_MSPI_IOMUX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + /* GPIO_PIN0_REG ~ GPIO_PIN62_REG*/ + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_GPIO_PINx(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + /* GPIO_FUNC0_IN_SEL_CFG_REG ~ GPIO_FUNC255_IN_SEL_CFG_REG & GPIO_FUNC0_OUT_SEL_CFG_REG ~ GPIO_FUNC0_IN_SEL_CFG_REG */ + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_GPIO_FUNC_IN(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_GPIO_FUNC_OUT(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; +_Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions"); + +/* Memory SPI Registers Context */ +#define N_REGS_SPI1_C_MEM_0() (((SPI1_MEM_C_INT_ENA_REG - DR_REG_FLASH_SPI1_BASE) / 4) + 1) +#define N_REGS_SPI1_C_MEM_1() (((SPI1_MEM_C_TIMING_CALI_REG - SPI1_MEM_C_TIMING_CALI_REG) / 4) + 1) +#define N_REGS_SPI0_C_MEM_0() (((SPI_MEM_C_DDR_REG - DR_REG_FLASH_SPI0_BASE) / 4) + 1) +#define N_REGS_SPI0_C_MEM_1() (((SPI_MEM_C_DOUT_MODE_REG - SPI_FMEM_C_PMS0_ATTR_REG) / 4) + 1) +#define N_REGS_SPI0_C_MEM_2() (((SPI_MEM_C_NAND_FLASH_SPI_SEQ31_REG - SPI_MEM_C_CLOCK_GATE_REG) / 4) + 1) +#define N_REGS_SPI0_C_MEM_3() (((SPI_MEM_C_REGISTERRND_ECO_LOW_REG - SPI_MEM_C_MMU_POWER_CTRL_REG) / 4) + 1) + +const regdma_entries_config_t flash_spimem_regs_retention[] = { + /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */ + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), DR_REG_FLASH_SPI1_BASE, DR_REG_FLASH_SPI1_BASE, N_REGS_SPI1_C_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi1_mem */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI1_MEM_C_INT_ENA_REG, SPI1_MEM_C_INT_ENA_REG, N_REGS_SPI1_C_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + + /* Note: SPI mem should not to write mmu SPI_MEM_MMU_ITEM_CONTENT_REG and SPI_MEM_MMU_ITEM_INDEX_REG */ + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), DR_REG_FLASH_SPI0_BASE, DR_REG_FLASH_SPI0_BASE, N_REGS_SPI0_C_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */ + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI_FMEM_C_PMS0_ATTR_REG, SPI_FMEM_C_PMS0_ATTR_REG, N_REGS_SPI0_C_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), SPI_MEM_C_CLOCK_GATE_REG, SPI_MEM_C_CLOCK_GATE_REG, N_REGS_SPI0_C_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x05), SPI_MEM_C_MMU_POWER_CTRL_REG, SPI_MEM_C_MMU_POWER_CTRL_REG, N_REGS_SPI0_C_MEM_3(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x06), SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CALI_UPDATE, SPI_MEM_C_TIMING_CALI_UPDATE_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; +_Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_FLASH_RETENTION_LINK_LEN, "Inconsistent Flash SPI Mem retention link length definitions"); + +#if CONFIG_SPIRAM +#define N_REGS_SPI0_S_MEM_0() (((SPI_MEM_S_INT_ENA_REG - SPI_MEM_S_CTRL_REG) / 4) + 1) +#define N_REGS_SPI0_S_MEM_1() (((SPI_MEM_S_CLOCK_GATE_REG - SPI_MEM_S_DDR_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_0() (((SPI1_MEM_S_INT_ENA_REG - SPI1_MEM_S_CMD_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_1() (((SPI1_MEM_S_DDR_REG - SPI1_MEM_S_DDR_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_2() (((SPI1_MEM_S_TIMING_CALI_REG - SPI1_MEM_S_TIMING_CALI_REG) / 4) + 1) + +const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN] = { + [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x00), SPI_MEM_S_CTRL_REG, SPI_MEM_S_CTRL_REG, N_REGS_SPI0_S_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* spi0_mem */ + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x01), SPI_MEM_S_DDR_REG, SPI_MEM_S_DDR_REG, N_REGS_SPI0_S_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x02), SPI1_MEM_S_CMD_REG, SPI1_MEM_S_CMD_REG, N_REGS_SPI1_S_MEM_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x03), SPI1_MEM_S_DDR_REG, SPI1_MEM_S_DDR_REG, N_REGS_SPI1_S_MEM_1(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SPIMEM_LINK(0x04), SPI1_MEM_S_TIMING_CALI_REG, SPI1_MEM_S_TIMING_CALI_REG, N_REGS_SPI1_S_MEM_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, +}; + +_Static_assert(ARRAY_SIZE(psram_spimem_regs_retention) == SPIMEM_PSRAM_RETENTION_LINK_LEN, "Inconsistent PSRAM SPI Mem retention link length definitions"); +#endif + +/* Systimer Registers Context */ +#define N_REGS_SYSTIMER_0() (((SYSTIMER_TARGET2_CONF_REG - SYSTIMER_TARGET0_HI_REG) / 4) + 1) +const regdma_entries_config_t systimer_regs_retention[] = { + // cnt value + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x00), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_UPDATE_M, SYSTIMER_TIMER_UNIT1_UPDATE_M, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_SYSTIMER_LINK(0x01), SYSTIMER_UNIT1_OP_REG, SYSTIMER_TIMER_UNIT1_VALUE_VALID, SYSTIMER_TIMER_UNIT1_VALUE_VALID, 0, 1), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x02), SYSTIMER_UNIT1_VALUE_HI_REG, SYSTIMER_UNIT1_LOAD_HI_REG, 2, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x03), SYSTIMER_UNIT1_LOAD_REG, SYSTIMER_TIMER_UNIT1_LOAD_M, SYSTIMER_TIMER_UNIT1_LOAD_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + + // target value + [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x04), SYSTIMER_TARGET0_HI_REG, SYSTIMER_TARGET0_HI_REG, N_REGS_SYSTIMER_0(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer target value & period */ + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x05), SYSTIMER_COMP0_LOAD_REG, SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_TIMER_COMP0_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x06), SYSTIMER_COMP1_LOAD_REG, SYSTIMER_TIMER_COMP1_LOAD, SYSTIMER_TIMER_COMP1_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SYSTIMER_LINK(0x07), SYSTIMER_COMP2_LOAD_REG, SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_TIMER_COMP2_LOAD, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, + + // conf & int value + [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x08), SYSTIMER_CONF_REG, SYSTIMER_CONF_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer work enable */ + [9] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_SYSTIMER_LINK(0x09), SYSTIMER_INT_ENA_REG, SYSTIMER_INT_ENA_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* Systimer intr enable */ +}; +_Static_assert(ARRAY_SIZE(systimer_regs_retention) == SYSTIMER_RETENTION_LINK_LEN, "Inconsistent Systimer retention link length definitions");