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Merge branch 'feature/add_esp32p4_esp_rom_support' into 'master'

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esp_rom: add esp32p4 esp_rom support

See merge request espressif/esp-idf!24703
This commit is contained in:
Armando (Dou Yiwen)
2023-07-13 19:08:42 +08:00
parent 1eba917545 3461449494
commit c7d8b06fd2
47 changed files with 6692 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -207,10 +207,6 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 3
config SOC_GDMA_SUPPORT_ETM
bool
default y
config SOC_ETM_GROUPS
int
default 1
components/soc/esp32p4/include/soc/ahb_dma_reg.h
+31 -31
View File
@@ -3148,13 +3148,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c4)
/** AHB_DMA_OUT_CRC_CLEAR_CH0_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_OUT_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG_M (AHB_DMA_OUT_CRC_CLEAR_CH0_REG_V << AHB_DMA_OUT_CRC_CLEAR_CH0_REG_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG_S 0
#define AHB_DMA_OUT_CRC_CLEAR_CH0 (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH0_M (AHB_DMA_OUT_CRC_CLEAR_CH0_V << AHB_DMA_OUT_CRC_CLEAR_CH0_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH0_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH0_S 0
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
* This register is used to store ch0 crc result
@@ -3277,13 +3277,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2ec)
/** AHB_DMA_OUT_CRC_CLEAR_CH1_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG_M (AHB_DMA_OUT_CRC_CLEAR_CH1_REG_V << AHB_DMA_OUT_CRC_CLEAR_CH1_REG_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG_S 0
#define AHB_DMA_OUT_CRC_CLEAR_CH1 (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH1_M (AHB_DMA_OUT_CRC_CLEAR_CH1_V << AHB_DMA_OUT_CRC_CLEAR_CH1_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH1_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH1_S 0
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
* This register is used to store ch0 crc result
@@ -3406,15 +3406,15 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x314)
/** AHB_DMA_OUT_CRC_CLEAR_CH2_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG_M (AHB_DMA_OUT_CRC_CLEAR_CH2_REG_V << AHB_DMA_OUT_CRC_CLEAR_CH2_REG_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG_S 0
#define AHB_DMA_OUT_CRC_CLEAR_CH2 (BIT(0))
#define AHB_DMA_OUT_CRC_CLEAR_CH2_M (AHB_DMA_OUT_CRC_CLEAR_CH2_V << AHB_DMA_OUT_CRC_CLEAR_CH2_S)
#define AHB_DMA_OUT_CRC_CLEAR_CH2_V 0x00000001U
#define AHB_DMA_OUT_CRC_CLEAR_CH2_S 0
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2 register
* This register is used to store ch0 crc result
*/
#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x318)
@@ -3535,13 +3535,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x33c)
/** AHB_DMA_IN_CRC_CLEAR_CH0_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG_M (AHB_DMA_IN_CRC_CLEAR_CH0_REG_V << AHB_DMA_IN_CRC_CLEAR_CH0_REG_S)
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH0_REG_S 0
#define AHB_DMA_IN_CRC_CLEAR_CH0 (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH0_M (AHB_DMA_IN_CRC_CLEAR_CH0_V << AHB_DMA_IN_CRC_CLEAR_CH0_S)
#define AHB_DMA_IN_CRC_CLEAR_CH0_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH0_S 0
/** AHB_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
* This register is used to store ch0 crc result
@@ -3664,13 +3664,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x364)
/** AHB_DMA_IN_CRC_CLEAR_CH1_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG_M (AHB_DMA_IN_CRC_CLEAR_CH1_REG_V << AHB_DMA_IN_CRC_CLEAR_CH1_REG_S)
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH1_REG_S 0
#define AHB_DMA_IN_CRC_CLEAR_CH1 (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH1_M (AHB_DMA_IN_CRC_CLEAR_CH1_V << AHB_DMA_IN_CRC_CLEAR_CH1_S)
#define AHB_DMA_IN_CRC_CLEAR_CH1_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH1_S 0
/** AHB_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
* This register is used to store ch0 crc result
@@ -3793,13 +3793,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x38c)
/** AHB_DMA_IN_CRC_CLEAR_CH2_REG : R/W; bitpos: [0]; default: 0;
/** AHB_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG_M (AHB_DMA_IN_CRC_CLEAR_CH2_REG_V << AHB_DMA_IN_CRC_CLEAR_CH2_REG_S)
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH2_REG_S 0
#define AHB_DMA_IN_CRC_CLEAR_CH2 (BIT(0))
#define AHB_DMA_IN_CRC_CLEAR_CH2_M (AHB_DMA_IN_CRC_CLEAR_CH2_V << AHB_DMA_IN_CRC_CLEAR_CH2_S)
#define AHB_DMA_IN_CRC_CLEAR_CH2_V 0x00000001U
#define AHB_DMA_IN_CRC_CLEAR_CH2_S 0
/** AHB_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
* This register is used to store ch0 crc result
components/soc/esp32p4/include/soc/axi_dma_reg.h
+30 -30
View File
@@ -827,13 +827,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AXI_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x50)
/** AXI_DMA_IN_CRC_CLEAR_CH0_REG : R/W; bitpos: [0]; default: 0;
/** AXI_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AXI_DMA_IN_CRC_CLEAR_CH0_REG (BIT(0))
#define AXI_DMA_IN_CRC_CLEAR_CH0_REG_M (AXI_DMA_IN_CRC_CLEAR_CH0_REG_V << AXI_DMA_IN_CRC_CLEAR_CH0_REG_S)
#define AXI_DMA_IN_CRC_CLEAR_CH0_REG_V 0x00000001U
#define AXI_DMA_IN_CRC_CLEAR_CH0_REG_S 0
#define AXI_DMA_IN_CRC_CLEAR_CH0 (BIT(0))
#define AXI_DMA_IN_CRC_CLEAR_CH0_M (AXI_DMA_IN_CRC_CLEAR_CH0_V << AXI_DMA_IN_CRC_CLEAR_CH0_S)
#define AXI_DMA_IN_CRC_CLEAR_CH0_V 0x00000001U
#define AXI_DMA_IN_CRC_CLEAR_CH0_S 0
/** AXI_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
* This register is used to store ch0 crc result
@@ -1711,13 +1711,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AXI_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb8)
/** AXI_DMA_IN_CRC_CLEAR_CH1_REG : R/W; bitpos: [0]; default: 0;
/** AXI_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AXI_DMA_IN_CRC_CLEAR_CH1_REG (BIT(0))
#define AXI_DMA_IN_CRC_CLEAR_CH1_REG_M (AXI_DMA_IN_CRC_CLEAR_CH1_REG_V << AXI_DMA_IN_CRC_CLEAR_CH1_REG_S)
#define AXI_DMA_IN_CRC_CLEAR_CH1_REG_V 0x00000001U
#define AXI_DMA_IN_CRC_CLEAR_CH1_REG_S 0
#define AXI_DMA_IN_CRC_CLEAR_CH1 (BIT(0))
#define AXI_DMA_IN_CRC_CLEAR_CH1_M (AXI_DMA_IN_CRC_CLEAR_CH1_V << AXI_DMA_IN_CRC_CLEAR_CH1_S)
#define AXI_DMA_IN_CRC_CLEAR_CH1_V 0x00000001U
#define AXI_DMA_IN_CRC_CLEAR_CH1_S 0
/** AXI_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
* This register is used to store ch0 crc result
@@ -2595,13 +2595,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AXI_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x120)
/** AXI_DMA_IN_CRC_CLEAR_CH2_REG : R/W; bitpos: [0]; default: 0;
/** AXI_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of rx crc result
*/
#define AXI_DMA_IN_CRC_CLEAR_CH2_REG (BIT(0))
#define AXI_DMA_IN_CRC_CLEAR_CH2_REG_M (AXI_DMA_IN_CRC_CLEAR_CH2_REG_V << AXI_DMA_IN_CRC_CLEAR_CH2_REG_S)
#define AXI_DMA_IN_CRC_CLEAR_CH2_REG_V 0x00000001U
#define AXI_DMA_IN_CRC_CLEAR_CH2_REG_S 0
#define AXI_DMA_IN_CRC_CLEAR_CH2 (BIT(0))
#define AXI_DMA_IN_CRC_CLEAR_CH2_M (AXI_DMA_IN_CRC_CLEAR_CH2_V << AXI_DMA_IN_CRC_CLEAR_CH2_S)
#define AXI_DMA_IN_CRC_CLEAR_CH2_V 0x00000001U
#define AXI_DMA_IN_CRC_CLEAR_CH2_S 0
/** AXI_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
* This register is used to store ch0 crc result
@@ -3441,13 +3441,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x188)
/** AXI_DMA_OUT_CRC_CLEAR_CH0_REG : R/W; bitpos: [0]; default: 0;
/** AXI_DMA_OUT_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG (BIT(0))
#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG_M (AXI_DMA_OUT_CRC_CLEAR_CH0_REG_V << AXI_DMA_OUT_CRC_CLEAR_CH0_REG_S)
#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG_V 0x00000001U
#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG_S 0
#define AXI_DMA_OUT_CRC_CLEAR_CH0 (BIT(0))
#define AXI_DMA_OUT_CRC_CLEAR_CH0_M (AXI_DMA_OUT_CRC_CLEAR_CH0_V << AXI_DMA_OUT_CRC_CLEAR_CH0_S)
#define AXI_DMA_OUT_CRC_CLEAR_CH0_V 0x00000001U
#define AXI_DMA_OUT_CRC_CLEAR_CH0_S 0
/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
* This register is used to store ch0 crc result
@@ -4287,13 +4287,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f0)
/** AXI_DMA_OUT_CRC_CLEAR_CH1_REG : R/W; bitpos: [0]; default: 0;
/** AXI_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG (BIT(0))
#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG_M (AXI_DMA_OUT_CRC_CLEAR_CH1_REG_V << AXI_DMA_OUT_CRC_CLEAR_CH1_REG_S)
#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG_V 0x00000001U
#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG_S 0
#define AXI_DMA_OUT_CRC_CLEAR_CH1 (BIT(0))
#define AXI_DMA_OUT_CRC_CLEAR_CH1_M (AXI_DMA_OUT_CRC_CLEAR_CH1_V << AXI_DMA_OUT_CRC_CLEAR_CH1_S)
#define AXI_DMA_OUT_CRC_CLEAR_CH1_V 0x00000001U
#define AXI_DMA_OUT_CRC_CLEAR_CH1_S 0
/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
* This register is used to store ch0 crc result
@@ -5133,13 +5133,13 @@ extern "C" {
* This register is used to clear ch0 crc result
*/
#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x258)
/** AXI_DMA_OUT_CRC_CLEAR_CH2_REG : R/W; bitpos: [0]; default: 0;
/** AXI_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
* This register is used to clear ch0 of tx crc result
*/
#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG (BIT(0))
#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG_M (AXI_DMA_OUT_CRC_CLEAR_CH2_REG_V << AXI_DMA_OUT_CRC_CLEAR_CH2_REG_S)
#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG_V 0x00000001U
#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG_S 0
#define AXI_DMA_OUT_CRC_CLEAR_CH2 (BIT(0))
#define AXI_DMA_OUT_CRC_CLEAR_CH2_M (AXI_DMA_OUT_CRC_CLEAR_CH2_V << AXI_DMA_OUT_CRC_CLEAR_CH2_S)
#define AXI_DMA_OUT_CRC_CLEAR_CH2_V 0x00000001U
#define AXI_DMA_OUT_CRC_CLEAR_CH2_S 0
/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
* This register is used to store ch0 crc result
components/soc/esp32p4/include/soc/soc_caps.h
+1 -1
View File
@@ -160,7 +160,7 @@
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_NUM_GROUPS_MAX 2
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
#define SOC_GDMA_SUPPORT_ETM 1 // Both AHB-DMA and AXI-DMA supports ETM
// #define SOC_GDMA_SUPPORT_ETM 1 // Both AHB-DMA and AXI-DMA supports ETM //TODO: IDF-6504
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups