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feat(mspi): support 120MHz flash and psram for esp32c61

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This commit is contained in:
Song Ruo Jing
2026-03-19 14:30:46 +00:00
committed by Zhang Wen Xu
parent 3b21e8e659
commit c7ae253b89
38 changed files with 135 additions and 272 deletions
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components/soc/esp32/include/soc/Kconfig.soc_caps.in
-16
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@@ -527,22 +527,6 @@ config SOC_SPI_MAX_PRE_DIVIDER
int
default 8192
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED
bool
default y
config SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
components/soc/esp32/include/soc/soc_caps.h
-6
View File
@@ -264,12 +264,6 @@
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_MAX_PRE_DIVIDER 8192
// Although ESP32 doesn't has memspi, but keep consistent with following chips.(This means SPI0/1)
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_host) ({(void)spi_host; 1;})