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feat(usb/h4): Add USB OTG host support for ESP32-H4

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- hal: add DWC OTG core LL (usb_dwc_ll.h) and USB wrap LL (usb_wrap_ll.h)
- soc: add DWC register map/cfg (usb_dwc_struct.h, usb_dwc_cfg.h) and caps
- soc/kconfig: enable SOC_USB_OTG_SUPPORTED=1, SOC_USB_OTG_PERIPH_NUM=1
- docs: add ESP32-H4 to usb_phy test app “Supported Targets”
- ld: export USB_WRAP symbol
- doxygen: include USB Host headers for H4 to emit .inc files
This commit is contained in:
igor.masar
2025-10-02 23:21:08 +02:00
parent eff16d4981
commit c74ce1c201
26 changed files with 2697 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+8
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@@ -35,6 +35,10 @@ config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_USB_OTG_SUPPORTED
bool
default y
config SOC_USB_SERIAL_JTAG_SUPPORTED
bool
default y
@@ -986,3 +990,7 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
config SOC_RCC_IS_INDEPENDENT
bool
default y
config SOC_USB_OTG_PERIPH_NUM
int
default 1
components/soc/esp32h4/include/soc/soc_caps.h
+4
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@@ -46,6 +46,7 @@
// #define SOC_BT_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_OTG_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12404
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
@@ -555,3 +556,6 @@
// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */
// #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)
components/soc/esp32h4/include/soc/usb_dwc_cfg.h
+89
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@@ -0,0 +1,89 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
Configuration Set ID: 1
*/
/* 3.1 Basic Config Parameters */
#define OTG_MODE 0
#define OTG_ARCHITECTURE 2
#define OTG_SINGLE_POINT 1
#define OTG_ENABLE_LPM 0
#define OTG_EN_DED_TX_FIFO 1
#define OTG_EN_DESC_DMA 1
#define OTG_MULTI_PROC_INTRPT 0
/* 3.2 USB Physical Layer Interface Parameters */
#define OTG_HSPHY_INTERFACE 0
#define OTG_FSPHY_INTERFACE 1
#define OTG_ENABLE_IC_USB 0
#define OTG_I2C_INTERFACE 0
#define OTG_ADP_SUPPORT 0
#define OTG_BC_SUPPORT 0
/* 3.3 Device Endpoint Configuration Parameters */
#define OTG_NUM_EPS 6
#define OTG_NUM_IN_EPS 5
#define OTG_NUM_CRL_EPS 0
/* 3.4 Host Endpoint Configuration Parameters */
#define OTG_NUM_HOST_CHAN 8
#define OTG_EN_PERIO_HOST 1
/* 3.5 Endpoint Channel FIFO Configuration Parameters */
#define OTG_DFIFO_DEPTH 256
#define OTG_DFIFO_DYNAMIC 1
#define OTG_RX_DFIFO_DEPTH 256
#define OTG_TX_HNPERIO_DFIFO_DEPTH 256
#define OTG_TX_NPERIO_DFIFO_DEPTH 256
#define OTG_TX_HPERIO_DFIFO_DEPTH 256
#define OTG_NPERIO_TX_QUEUE_DEPTH 4
#define OTG_PERIO_TX_QUEUE_DEPTH 8
/* 3.6 Additional Configuration Options Parameters */
#define OTG_TRANS_COUNT_WIDTH 16
#define OTG_PACKET_COUNT_WIDTH 7
#define OTG_RM_OPT_FEATURES 1
#define OTG_EN_PWROPT 1
#define OTG_SYNC_RESET_TYPE 0
#define OTG_EN_IDDIG_FILTER 1
#define OTG_EN_VBUSVALID_FILTER 1
#define OTG_EN_A_VALID_FILTER 1
#define OTG_EN_B_VALID_FILTER 1
#define OTG_EN_SESSIONEND_FILTER 1
#define OTG_EXCP_CNTL_XFER_FLOW 1
#define OTG_PWR_CLAMP 0
#define OTG_PWR_SWITCH_POLARITY 0
/* 3.7 Endpoint Direction Parameters */
#define OTG_EP_DIR_1 0
#define OTG_EP_DIR_2 0
#define OTG_EP_DIR_3 0
#define OTG_EP_DIR_4 0
#define OTG_EP_DIR_5 0
#define OTG_EP_DIR_6 0
/* 3.8 Device Periodic FIFO Depth Parameters */
/* 3.9 Device IN Endpoint FIFO Depth Parameters */
#define OTG_TX_DINEP_DFIFO_DEPTH_1 256
#define OTG_TX_DINEP_DFIFO_DEPTH_2 256
#define OTG_TX_DINEP_DFIFO_DEPTH_3 256
#define OTG_TX_DINEP_DFIFO_DEPTH_4 256
/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
#define U2UB_EN 0
#ifdef __cplusplus
}
#endif
components/soc/esp32h4/include/soc/usb_dwc_struct.h
+1173
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File diff suppressed because it is too large Load Diff
components/soc/esp32h4/include/soc/usb_struct.h
+109
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@@ -0,0 +1,109 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* USB IN EP Register block type */
typedef struct usb_in_ep_reg {
volatile uint32_t diepctl;
uint32_t reserved;
volatile uint32_t diepint;
uint32_t reserved1;
volatile uint32_t dieptsiz;
volatile uint32_t diepdma;
volatile uint32_t dtxfsts;
uint32_t reserved2;
} usb_in_endpoint_t;
/* USB OUT EP Register block type */
typedef struct usb_out_ep_reg {
volatile uint32_t doepctl;
uint32_t reserved;
volatile uint32_t doepint;
uint32_t reserved1;
volatile uint32_t doeptsiz;
volatile uint32_t doepdma;
uint32_t reserved2;
uint32_t reserved3;
} usb_out_endpoint_t;
typedef struct usb_dev_t {
volatile uint32_t gotgctl;
volatile uint32_t gotgint;
volatile uint32_t gahbcfg;
volatile uint32_t gusbcfg;
volatile uint32_t grstctl;
volatile uint32_t gintsts;
volatile uint32_t gintmsk;
volatile uint32_t grxstsr;
volatile uint32_t grxstsp;
volatile uint32_t grxfsiz;
volatile uint32_t gnptxfsiz;
volatile uint32_t gnptxsts;
uint32_t reserved_0x0030_0x0040[4];
volatile uint32_t gsnpsid;
volatile uint32_t ghwcfg1;
volatile uint32_t ghwcfg2;
volatile uint32_t ghwcfg3;
volatile uint32_t ghwcfg4;
uint32_t reserved_0x0054_0x005c[2];
volatile uint32_t gdfifocfg;
uint32_t reserved_0x0060_0x0100[40];
volatile uint32_t hptxfsiz;
volatile uint32_t dieptxf[4];
uint32_t reserved_0x0114_0x0140[11];
uint32_t reserved_0x0140_0x0400[176];
volatile uint32_t hcfg;
volatile uint32_t hfir;
volatile uint32_t hfnum;
uint32_t reserved0x40C;
volatile uint32_t hptxsts;
volatile uint32_t haint;
volatile uint32_t haintmsk;
volatile uint32_t hflbaddr;
uint32_t reserved0x0420_0x0440[8];
volatile uint32_t hprt;
uint32_t reserved_0x0444_0x0500[47];
volatile uint32_t host_chan_regs[128];
uint32_t reserved_0x0700_0x0800[64];
volatile uint32_t dcfg;
volatile uint32_t dctl;
volatile uint32_t dsts;
uint32_t reserved0x80c;
volatile uint32_t diepmsk;
volatile uint32_t doepmsk;
volatile uint32_t daint;
volatile uint32_t daintmsk;
uint32_t reserved_0x0820_0x0828[2];
volatile uint32_t dvbusdis;
volatile uint32_t dvbuspulse;
volatile uint32_t dthrctl;
volatile uint32_t dtknqr4_fifoemptymsk;
uint32_t reserved_0x0838_0x0900[50];
usb_in_endpoint_t in_ep_reg[7];
uint32_t reserved_0x09e0_0x0b00[72];
usb_out_endpoint_t out_ep_reg[7];
uint32_t reserved_0x0be0_0x0d00[72];
uint32_t reserved_0x0d00_0x0e00[64];
uint32_t pcgctrl;
uint32_t reserved_0x0e04;
uint8_t reserved8[0x1000 - 0xe08];
uint32_t fifo[16][0x400];
uint8_t reserved0x11000[0x20000 - 0x11000];
uint32_t dbg_fifo[0x20000];
} usb_dev_t;
extern usb_dev_t USB0;
#ifdef __cplusplus
}
#endif
components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld
+1
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@@ -38,6 +38,7 @@ PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 );
PROVIDE ( ZERO_DET = 0x60029000 );
PROVIDE ( USB_OTG_FS_CORE0 = 0x60040000 );
PROVIDE ( USB_OTG_FS_CORE1 = 0x6007F000 );
PROVIDE ( USB_DWC = 0x60040000 );
PROVIDE ( USB_WRAP = 0x60080000 );
PROVIDE ( TIMERG0 = 0x60090000 );
PROVIDE ( TIMERG1 = 0x60091000 );
components/soc/esp32h4/ld/esp32h4.peripherals.ld
+1
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@@ -38,6 +38,7 @@ PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 );
PROVIDE ( ZERO_DET = 0x60029000 );
PROVIDE ( USB_OTG_FS_CORE0 = 0x60040000 );
PROVIDE ( USB_OTG_FS_CORE1 = 0x6007F000 );
PROVIDE ( USB_DWC = 0x60040000 );
PROVIDE ( USB_WRAP = 0x60080000 );
PROVIDE ( TIMERG0 = 0x60090000 );
PROVIDE ( TIMERG1 = 0x60091000 );
components/soc/esp32h4/usb_dwc_periph.c
+48
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@@ -0,0 +1,48 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/gpio_sig_map.h"
#include "soc/interrupts.h"
#include "soc/usb_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_OUT_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_OUT_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_OUT_IDX,
.drvvbus = USB_OTG_DRVVBUS_OUT_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_OUT_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_OUT_IDX,
};
static const usb_internal_phy_io_t internal_phy_io = {
.dp = 21,
.dm = 22,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = NULL,
.otg_signals = &otg_signals,
.internal_phy_io = &internal_phy_io,
.supported_phys = USB_PHY_INST_FSLS_INTERN_0,
.irq = ETS_USB_OTG11_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};