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fix(esp_rom): sync spi_flash_disable/enable_cache patches to rom implementation

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This commit is contained in:
wuzhenghui
2026-03-09 21:21:24 +08:00
parent 582875df53
commit c59c3a2c8d
11 changed files with 44 additions and 18 deletions
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components/esp_rom/esp32c2/ld/esp32c2.rom.ld
+2 -2
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@@ -139,8 +139,8 @@ PROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );
PROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 ); PROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );
PROVIDE( spi_flash_cache2phys = 0x400001ac ); PROVIDE( spi_flash_cache2phys = 0x400001ac );
PROVIDE( spi_flash_phys2cache = 0x400001b0 ); PROVIDE( spi_flash_phys2cache = 0x400001b0 );
PROVIDE( spi_flash_disable_cache = 0x400001b4 ); PROVIDE( rom_spi_flash_disable_cache = 0x400001b4 );
PROVIDE( spi_flash_restore_cache = 0x400001b8 ); PROVIDE( rom_spi_flash_restore_cache = 0x400001b8 );
PROVIDE( spi_flash_cache_enabled = 0x400001bc ); PROVIDE( spi_flash_cache_enabled = 0x400001bc );
PROVIDE( spi_flash_enable_cache = 0x400001c0 ); PROVIDE( spi_flash_enable_cache = 0x400001c0 );
PROVIDE( spi_cache_mode_switch = 0x400001c4 ); PROVIDE( spi_cache_mode_switch = 0x400001c4 );
components/esp_rom/esp32c3/ld/esp32c3.rom.ld
+2 -2
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@@ -144,8 +144,8 @@ PROVIDE( spi_flash_check_and_flush_cache = 0x400001b4 );
PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 ); PROVIDE( spi_flash_mmap_get_free_pages = 0x400001b8 );
PROVIDE( spi_flash_cache2phys = 0x400001bc ); PROVIDE( spi_flash_cache2phys = 0x400001bc );
PROVIDE( spi_flash_phys2cache = 0x400001c0 ); PROVIDE( spi_flash_phys2cache = 0x400001c0 );
PROVIDE( spi_flash_disable_cache = 0x400001c4 ); PROVIDE( rom_spi_flash_disable_cache = 0x400001c4 );
PROVIDE( spi_flash_restore_cache = 0x400001c8 ); PROVIDE( rom_spi_flash_restore_cache = 0x400001c8 );
PROVIDE( spi_flash_cache_enabled = 0x400001cc ); PROVIDE( spi_flash_cache_enabled = 0x400001cc );
PROVIDE( spi_flash_enable_cache = 0x400001d0 ); PROVIDE( spi_flash_enable_cache = 0x400001d0 );
PROVIDE( spi_cache_mode_switch = 0x400001d4 ); PROVIDE( spi_cache_mode_switch = 0x400001d4 );
components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
spi_flash_disable_cache = 0x40000204; rom_spi_flash_disable_cache = 0x40000204;
spi_flash_restore_cache = 0x40000208; rom_spi_flash_restore_cache = 0x40000208;
spi_flash_cache_enabled = 0x4000020c; spi_flash_cache_enabled = 0x4000020c;
spi_flash_enable_cache = 0x40000210; spi_flash_enable_cache = 0x40000210;
esp_enable_cache_flash_wrap = 0x40000214; esp_enable_cache_flash_wrap = 0x40000214;
components/esp_rom/esp32c6/ld/esp32c6.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
spi_flash_disable_cache = 0x400001f0; rom_spi_flash_disable_cache = 0x400001f0;
spi_flash_restore_cache = 0x400001f4; rom_spi_flash_restore_cache = 0x400001f4;
spi_flash_cache_enabled = 0x400001f8; spi_flash_cache_enabled = 0x400001f8;
esp_enable_cache_flash_wrap = 0x40000200; esp_enable_cache_flash_wrap = 0x40000200;
components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
spi_flash_disable_cache = 0x40000204; rom_spi_flash_disable_cache = 0x40000204;
spi_flash_restore_cache = 0x40000208; rom_spi_flash_restore_cache = 0x40000208;
spi_flash_cache_enabled = 0x4000020c; spi_flash_cache_enabled = 0x4000020c;
spi_flash_enable_cache = 0x40000210; spi_flash_enable_cache = 0x40000210;
esp_enable_cache_flash_wrap = 0x40000214; esp_enable_cache_flash_wrap = 0x40000214;
components/esp_rom/esp32h2/ld/esp32h2.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
spi_flash_disable_cache = 0x400001e8; rom_spi_flash_disable_cache = 0x400001e8;
spi_flash_restore_cache = 0x400001ec; rom_spi_flash_restore_cache = 0x400001ec;
spi_flash_cache_enabled = 0x400001f0; spi_flash_cache_enabled = 0x400001f0;
esp_enable_cache_flash_wrap = 0x400001f8; esp_enable_cache_flash_wrap = 0x400001f8;
components/esp_rom/esp32h21/ld/esp32h21.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
spi_flash_disable_cache = 0x400001e8; rom_spi_flash_disable_cache = 0x400001e8;
spi_flash_restore_cache = 0x400001ec; rom_spi_flash_restore_cache = 0x400001ec;
spi_flash_cache_enabled = 0x400001f0; spi_flash_cache_enabled = 0x400001f0;
spi_flash_enable_cache = 0x400001f4; spi_flash_enable_cache = 0x400001f4;
esp_enable_cache_flash_wrap = 0x400001f8; esp_enable_cache_flash_wrap = 0x400001f8;
components/esp_rom/esp32h4/ld/esp32h4.rom.spiflash.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/ ***************************************/
/* Functions */ /* Functions */
spi_flash_disable_cache = 0x400001f8; rom_spi_flash_disable_cache = 0x400001f8;
spi_flash_restore_cache = 0x400001fc; rom_spi_flash_restore_cache = 0x400001fc;
spi_flash_cache_enabled = 0x40000200; spi_flash_cache_enabled = 0x40000200;
spi_flash_enable_cache = 0x40000204; spi_flash_enable_cache = 0x40000204;
esp_enable_cache_flash_wrap = 0x40000208; esp_enable_cache_flash_wrap = 0x40000208;
components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+2 -2
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@@ -196,8 +196,8 @@ PROVIDE( spi_flash_check_and_flush_cache = 0x40000bdc );
PROVIDE( spi_flash_mmap_get_free_pages = 0x40000be8 ); PROVIDE( spi_flash_mmap_get_free_pages = 0x40000be8 );
PROVIDE( spi_flash_cache2phys = 0x40000bf4 ); /* patched when XIP */ PROVIDE( spi_flash_cache2phys = 0x40000bf4 ); /* patched when XIP */
PROVIDE( spi_flash_phys2cache = 0x40000c00 ); /* patched when XIP */ PROVIDE( spi_flash_phys2cache = 0x40000c00 ); /* patched when XIP */
PROVIDE( spi_flash_disable_cache = 0x40000c0c ); PROVIDE( rom_spi_flash_disable_cache = 0x40000c0c );
PROVIDE( spi_flash_restore_cache = 0x40000c18 ); PROVIDE( rom_spi_flash_restore_cache = 0x40000c18 );
PROVIDE( spi_flash_cache_enabled = 0x40000c24 ); PROVIDE( spi_flash_cache_enabled = 0x40000c24 );
PROVIDE( spi_flash_enable_cache = 0x40000c30 ); PROVIDE( spi_flash_enable_cache = 0x40000c30 );
PROVIDE( spi_cache_mode_switch = 0x40000c3c ); PROVIDE( spi_cache_mode_switch = 0x40000c3c );
components/esp_rom/patches/esp_rom_spiflash.c
+24
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@@ -13,6 +13,9 @@
#include "soc/spi_mem_reg.h" #include "soc/spi_mem_reg.h"
#endif #endif
#if SOC_BRANCH_PREDICTOR_SUPPORTED
#include "riscv/rv_utils.h"
#endif
#include "esp_rom_spiflash.h" #include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h" #include "esp32/rom/spi_flash.h"
@@ -809,3 +812,24 @@ void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const
} }
#endif // IDF_TARGET #endif // IDF_TARGET
#if CONFIG_SPI_FLASH_ROM_IMPL
extern void rom_spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
{
#if SOC_BRANCH_PREDICTOR_SUPPORTED
//branch predictor will start cache request as well
rv_utils_dis_branch_predictor();
#endif
rom_spi_flash_disable_cache(cpuid, saved_state);
}
extern void rom_spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
{
rom_spi_flash_restore_cache(cpuid, saved_state);
#if SOC_BRANCH_PREDICTOR_SUPPORTED
rv_utils_en_branch_predictor();
#endif
}
#endif
components/spi_flash/cache_utils.c
+2
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@@ -325,6 +325,7 @@ void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
#endif #endif
} }
#if !CONFIG_SPI_FLASH_ROM_IMPL
void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state) void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
{ {
#if SOC_BRANCH_PREDICTOR_SUPPORTED #if SOC_BRANCH_PREDICTOR_SUPPORTED
@@ -346,6 +347,7 @@ bool IRAM_ATTR spi_flash_cache_enabled(void)
{ {
return cache_hal_is_cache_enabled(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); return cache_hal_is_cache_enabled(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
} }
#endif
#if CONFIG_IDF_TARGET_ESP32S2 #if CONFIG_IDF_TARGET_ESP32S2
IRAM_ATTR void esp_config_instruction_cache_mode(void) IRAM_ATTR void esp_config_instruction_cache_mode(void)