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Merge branch 'refactor/mcpwm_independent_hal_v6.0' into 'release/v6.0'

Browse Source 
refactor(mcpwm): make mcpwm_hal independent & cleanup soc_caps (Backport v6.0)

See merge request espressif/esp-idf!43103
This commit is contained in:
morris
2025-11-12 14:39:00 +08:00
parent 734e600d22 ed64a767ef
commit c4f9d7177c
57 changed files with 1041 additions and 1216 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/CMakeLists.txt
-4
View File
@@ -132,10 +132,6 @@ if(CONFIG_SOC_PARLIO_SUPPORTED)
list(APPEND srcs "${target_folder}/parlio_periph.c")
endif()
if(CONFIG_SOC_MCPWM_SUPPORTED)
list(APPEND srcs "${target_folder}/mcpwm_periph.c")
endif()
if(CONFIG_SOC_MPI_SUPPORTED)
list(APPEND srcs "${target_folder}/mpi_periph.c")
endif()
components/soc/esp32/include/soc/Kconfig.soc_caps.in
-40
View File
@@ -455,46 +455,6 @@ config SOC_LEDC_TIMER_BIT_WIDTH
int
default 20
config SOC_MCPWM_GROUPS
int
default 2
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MMU_PERIPH_NUM
int
default 2
components/soc/esp32/include/soc/soc_caps.h
-12
View File
@@ -238,18 +238,6 @@
#define SOC_LEDC_CHANNEL_NUM (8)
#define SOC_LEDC_TIMER_BIT_WIDTH (20)
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of GPIO fault signals that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
/*-------------------------- MMU CAPS ----------------------------------------*/
#define SOC_MMU_PERIPH_NUM 2
#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM 3
components/soc/esp32/mcpwm_periph.c
-152
View File
@@ -1,152 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
[1] = {
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_IN_IDX
}
}
}
}
};
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-44
View File
@@ -867,50 +867,6 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MCPWM_GROUPS
int
default 1
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
-11
View File
@@ -353,17 +353,6 @@
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS 1U ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP 3 ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP 3 ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR 2 ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR 2 ///< The number of generators that each operator has
#define SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR 2 ///< The number of event comparators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR 2 ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP 3 ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP 1 ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3 ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3 ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1 ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1 ///< Support event comparator (based on ETM)
components/soc/esp32c5/mcpwm_periph.c
-133
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@@ -1,133 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module_name = "MCPWM0",
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
}
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 68
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2)
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
[0] = {
.regdma_entry_array = mcpwm_regs_retention,
.array_size = ARRAY_SIZE(mcpwm_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
};
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-40
View File
@@ -811,46 +811,6 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MCPWM_GROUPS
int
default 1
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+1 -10
View File
@@ -327,16 +327,7 @@
#define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
components/soc/esp32c6/mcpwm_periph.c
-133
View File
@@ -1,133 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module_name = "MCPWM0",
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 61
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2)
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
[0] = {
.regdma_entry_array = mcpwm_regs_retention,
.array_size = ARRAY_SIZE(mcpwm_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
};
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
-40
View File
@@ -803,46 +803,6 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MCPWM_GROUPS
int
default 1
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+1 -10
View File
@@ -340,16 +340,7 @@
#define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
components/soc/esp32h2/mcpwm_periph.c
-133
View File
@@ -1,133 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module_name = "MCPWM0",
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 61
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2)
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
[0] = {
.regdma_entry_array = mcpwm_regs_retention,
.array_size = ARRAY_SIZE(mcpwm_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
};
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-44
View File
@@ -1199,50 +1199,6 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MCPWM_GROUPS
int
default 2
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+1 -11
View File
@@ -436,17 +436,7 @@
#define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR (2) ///< The number of event comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR (1) ///< Support event comparator (based on ETM)
components/soc/esp32p4/mcpwm_periph.c
-208
View File
@@ -1,208 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_PAD_IN_IDX
}
}
},
[1] = {
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_PAD_IN_IDX
}
}
}
}
};
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 68
#define MCPWM_RETENTION_REGS_BASE(i) REG_MCPWM_BASE(i)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \
/* backup stage: save configuration registers \
restore stage: restore the configuration registers */ \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \
REGDMA_MCPWM_LINK(0x00), \
MCPWM_RETENTION_REGS_BASE(mcpwm_port), \
MCPWM_RETENTION_REGS_BASE(mcpwm_port), \
MCPWM_RETENTION_REGS_CNT, 0, 0, \
mcpwm_regs_map[0], mcpwm_regs_map[1], \
mcpwm_regs_map[2], mcpwm_regs_map[3]), \
.owner = ENTRY(0)}, \
/* restore stage: trigger a forced update of all active registers*/ \
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), \
MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \
.owner = ENTRY(0) }, \
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), \
MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \
.owner = ENTRY(0) }, \
};
static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0);
static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1);
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
[0] = {
.regdma_entry_array = mcpwm0_regs_retention,
.array_size = ARRAY_SIZE(mcpwm0_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
[1] = {
.regdma_entry_array = mcpwm1_regs_retention,
.array_size = ARRAY_SIZE(mcpwm1_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM1
},
};
#endif //SOC_MCPWM_SUPPORT_SLEEP_RETENTION
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
-40
View File
@@ -595,46 +595,6 @@ config SOC_LEDC_SUPPORT_FADE_STOP
bool
default y
config SOC_MCPWM_GROUPS
int
default 2
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
+1 -11
View File
@@ -245,17 +245,7 @@
#define SOC_LEDC_TIMER_BIT_WIDTH (14)
#define SOC_LEDC_SUPPORT_FADE_STOP (1)
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
/*-------------------------- MCPWM CAPS ---------------------------------------*/
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
/*-------------------------- MMU CAPS ----------------------------------------*/
components/soc/esp32s3/mcpwm_periph.c
-152
View File
@@ -1,152 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
[1] = {
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_IN_IDX
}
}
}
}
};
components/soc/include/soc/mcpwm_periph.h
-59
View File
@@ -1,59 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/regdma.h"
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
#include "soc/retention_periph_defs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_MCPWM_SUPPORTED
typedef struct {
struct {
const char *module_name;
const int irq_id;
struct {
struct {
const uint32_t pwm_sig;
} generators[SOC_MCPWM_GENERATORS_PER_OPERATOR];
} operators[SOC_MCPWM_OPERATORS_PER_GROUP];
struct {
const uint32_t fault_sig;
} gpio_faults[SOC_MCPWM_GPIO_FAULTS_PER_GROUP];
struct {
const uint32_t cap_sig;
} captures[SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER];
struct {
const uint32_t sync_sig;
} gpio_synchros[SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP];
} groups[SOC_MCPWM_GROUPS];
} mcpwm_signal_conn_t;
extern const mcpwm_signal_conn_t mcpwm_periph_signals;
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
typedef struct {
const regdma_entries_config_t *regdma_entry_array;
uint32_t array_size;
const periph_retention_module_t retention_module;
} mcpwm_reg_retention_info_t;
extern const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS];
#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION
#endif // SOC_MCPWM_SUPPORTED
#ifdef __cplusplus
}
#endif