diff --git a/components/esp_driver_isp/src/isp_core.c b/components/esp_driver_isp/src/isp_core.c
index 854233c6064..49fab4c3e0a 100644
--- a/components/esp_driver_isp/src/isp_core.c
+++ b/components/esp_driver_isp/src/isp_core.c
@@ -43,8 +43,8 @@ static esp_err_t s_isp_claim_processor(isp_processor_t *proc)
             s_platform.processors[i] = proc;
             proc->proc_id = i;
             PERIPH_RCC_ATOMIC() {
-                isp_ll_enable_module_clock(proc->hal.hw, true);
-                isp_ll_reset_module_clock(proc->hal.hw);
+                isp_ll_enable_module_clock(true);
+                isp_ll_reset_module_clock();
             }
             break;
         }
@@ -64,7 +64,7 @@ static esp_err_t s_isp_declaim_processor(isp_processor_t *proc)
     _lock_acquire(&s_platform.mutex);
     s_platform.processors[proc->proc_id] = NULL;
     PERIPH_RCC_ATOMIC() {
-        isp_ll_enable_module_clock(proc->hal.hw, false);
+        isp_ll_enable_module_clock(false);
     }
     _lock_release(&s_platform.mutex);
 
@@ -110,14 +110,15 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_
     if (out_clk_freq_hz != proc_config->clk_hz) {
         ESP_LOGW(TAG, "precision loss, real output frequency: %"PRIu32"Hz", out_clk_freq_hz);
     }
-    ;
-    isp_hal_init(&proc->hal, proc->proc_id);
+
     esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
     PERIPH_RCC_ATOMIC() {
-        isp_ll_select_clk_source(proc->hal.hw, clk_src);
-        isp_ll_set_clock_div(proc->hal.hw, &clk_div);
+        isp_ll_select_clk_source(clk_src);
+        isp_ll_set_clock_div(&clk_div);
     }
 
+    isp_hal_init(&proc->hal, proc->proc_id);
+
     atomic_init(&proc->isp_fsm, ISP_FSM_INIT);
     atomic_init(&proc->bf_fsm, ISP_FSM_INIT);
     atomic_init(&proc->blc_fsm, ISP_FSM_INIT);
diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h
index 644c41b9db6..4ff69196b5c 100644
--- a/components/hal/esp32p4/include/hal/isp_ll.h
+++ b/components/hal/esp32p4/include/hal/isp_ll.h
@@ -252,10 +252,9 @@ typedef enum {
 /**
  * @brief Enable the bus clock for ISP module
  *
- * @param hw    Hardware instance address
  * @param en    enable / disable
  */
-static inline void isp_ll_enable_module_clock(isp_dev_t *hw, bool en)
+static inline void isp_ll_enable_module_clock(bool en)
 {
     HP_SYS_CLKRST.peri_clk_ctrl25.reg_isp_clk_en = en;
 }
@@ -266,10 +265,8 @@ static inline void isp_ll_enable_module_clock(isp_dev_t *hw, bool en)
 
 /**
  * @brief Reset the ISP module
- *
- * @param hw    Hardware instance address
  */
-static inline void isp_ll_reset_module_clock(isp_dev_t *hw)
+static inline void isp_ll_reset_module_clock(void)
 {
     HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_isp = 1;
     HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_isp = 0;
@@ -282,20 +279,19 @@ static inline void isp_ll_reset_module_clock(isp_dev_t *hw)
 /**
  * @brief Select ISP clock source
  *
- * @param hw       Hardware instance address
  * @param clk_src  clock source, see valid sources in type `soc_periph_isp_clk_src_t`
  */
-static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_src_t clk_src)
+static inline void isp_ll_select_clk_source(soc_periph_isp_clk_src_t clk_src)
 {
     uint32_t clk_val = 0;
     switch (clk_src) {
     case ISP_CLK_SRC_XTAL:
         clk_val = 0;
         break;
-    case ISP_CLK_SRC_PLL160:
+    case ISP_CLK_SRC_PLL240:
         clk_val = 1;
         break;
-    case ISP_CLK_SRC_PLL240:
+    case ISP_CLK_SRC_PLL160:
         clk_val = 2;
         break;
     default:
@@ -313,10 +309,9 @@ static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_sr
 /**
  * @brief Set ISP clock div
  *
- * @param hw     Hardware instance address
  * @param div    Clock division with integral and decimal part
  */
-static inline void isp_ll_set_clock_div(isp_dev_t *hw, const hal_utils_clk_div_t *clk_div)
+static inline void isp_ll_set_clock_div(const hal_utils_clk_div_t *clk_div)
 {
     HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= ISP_LL_TX_MAX_CLK_INT_DIV);
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl26, reg_isp_clk_div_num, clk_div->integer - 1);
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 209e02c4b6d..9f2c94a083e 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -562,7 +562,7 @@ typedef enum {
  * @brief Type of ISP clock source.
  */
 typedef enum {
-    ISP_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,      /*!< Select SOC_MOD_CLK_PLL_F160M as ISP source clock */
+    ISP_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M,      /*!< Select SOC_MOD_CLK_PLL_F240M as ISP source clock */
     ISP_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,              /*!< Select SOC_MOD_CLK_XTAL as ISP source clock */
     ISP_CLK_SRC_PLL160 = SOC_MOD_CLK_PLL_F160M,       /*!< Select SOC_MOD_CLK_PLL_F160M as ISP source clock */
     ISP_CLK_SRC_PLL240 = SOC_MOD_CLK_PLL_F240M,       /*!< Select SOC_MOD_CLK_PLL_F240M as ISP source clock */
diff --git a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
index 6a3df077fa9..8dcaf587a09 100644
--- a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
+++ b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
@@ -419,7 +419,7 @@ void app_main(void)
         .v_res = display_v_res,
         .lane_bit_rate_mbps = EXAMPLE_MIPI_CSI_LANE_BITRATE_MBPS,
         .input_data_color_type = CAM_CTLR_COLOR_RAW8,
-        .output_data_color_type = CAM_CTLR_COLOR_RGB565,
+        .output_data_color_type = CAM_CTLR_COLOR_RAW8,
         .data_lane_num = 2,
         .byte_swap_en = false,
         .queue_items = 1,