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https://github.com/espressif/esp-idf.git
synced 2026-10-01 10:40:47 +03:00
refactor(system): guard WDT with SoC capability macros
Wrap MWDT-related code under SOC_WDT_SUPPORTED so targets without a main watchdog can compile. Add SOC_RTC_WDT_SUPPORTED for RTC watchdog usage (bootloader, slow-clock paths) and regenerate Kconfig.soc_caps.in. Bootloader RWDT setup stays under SOC_RTC_WDT_SUPPORTED; MWDT flashboot teardown stays under SOC_WDT_SUPPORTED. ESP_INT_WDT, ESP_TASK_WDT_EN, and BOOTLOADER_WDT_ENABLE depend on SOC_WDT_SUPPORTED where applicable. Build xt_wdt.c only when SOC_XT_WDT_SUPPORTED. Provide no-op panic WDT helpers when SOC_WDT_SUPPORTED is disabled.
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -33,12 +33,15 @@
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#include "soc/extmem_reg.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/soc_caps.h"
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#include "esp_efuse.h"
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#include "hal/mmu_hal.h"
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#include "hal/cache_hal.h"
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ESP_LOG_ATTR_TAG(TAG, "boot.esp32s2");
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#if SOC_RTC_WDT_SUPPORTED
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static void wdt_reset_cpu0_info_enable(void)
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{
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DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_ASSIST_DEBUG);
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@@ -100,11 +103,14 @@ static void bootloader_super_wdt_auto_feed(void)
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{
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REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
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}
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#endif // SOC_RTC_WDT_SUPPORTED
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esp_err_t bootloader_init(void)
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{
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esp_err_t ret = ESP_OK;
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#if SOC_RTC_WDT_SUPPORTED
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bootloader_super_wdt_auto_feed();
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#endif
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// protect memory region
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// In RAM_APP, memory will be initialized in `call_start_cpu0`
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@@ -163,10 +169,14 @@ esp_err_t bootloader_init(void)
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}
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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#if SOC_RTC_WDT_SUPPORTED
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// check whether a WDT reset happened
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bootloader_check_wdt_reset();
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#endif
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#if SOC_RTC_WDT_SUPPORTED || SOC_WDT_SUPPORTED
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// config WDT
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bootloader_config_wdt();
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#endif
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// enable RNG early entropy source
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bootloader_enable_random();
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