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feat(i2c): support i2c sleep retention on esp32h21

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This commit is contained in:
Chen Chen
2026-09-15 15:12:46 +08:00
parent 4d7f280139
commit c4c83bc041
4 changed files with 76 additions and 7 deletions
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components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+4
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@@ -555,6 +555,10 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_I2S_HW_VERSION_2
bool
default y
components/soc/esp32h21/include/soc/soc.h
+4 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -16,16 +16,15 @@
#define PRO_CPU_NUM (0)
// TODO: IDF-11856
#define DR_REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define DR_REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000)
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000)
#define DR_REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define DR_REG_UART_AHB_BASE(i) (DR_REG_UART0_BASE + (i) * 0x10000)
#define DR_UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define DR_REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on H21
#define DR_REG_I2S_BASE(i) (DR_REG_I2S0_BASE) // only one I2S on H21
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i)*0x1000)
#define DR_REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000)
#define DR_REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)
#define DR_REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000)
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
components/soc/esp32h21/include/soc/soc_caps.h
+1 -1
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@@ -246,7 +246,7 @@
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: [ESP32H21] IDF-11579
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_HW_VERSION_2 (1)