Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-09-22 13:01:16 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(esp_eth): fixes EMAC MDC out of the range issue

Browse Source 
Closes https://github.com/espressif/esp-idf/issues/17984
This commit is contained in:
Ondrej Kosta
2025-12-11 11:20:53 +01:00
parent 03f2b26253
commit c422590235
10 changed files with 77 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
components/esp_eth/include/esp_eth_mac_esp.h
View File

@@ -182,6 +182,7 @@ typedef struct {
#if !SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
eth_mac_clock_config_t clock_config_out_in; /*!< EMAC input clock configuration for internally generated output clock (when output clock is looped back externally) */
#endif //SOC_EMAC_RMII_CLK_OUT_INTERNAL_LOOPBACK
int32_t mdc_freq_hz; /*!< EMAC MDC frequency range limit, if set to 0 or a negative value, the driver will set the CSR clock range up to 2.5 MHz */
} eth_esp32_emac_config_t;
/**
@@ -235,6 +236,7 @@ typedef enum {
}, \
.dma_burst_len = ETH_DMA_BURST_LEN_32, \
.intr_priority = 0, \
.mdc_freq_hz = 0, \
}
#elif CONFIG_IDF_TARGET_ESP32P4
#define ETH_ESP32_EMAC_DEFAULT_CONFIG() \
@@ -255,6 +257,7 @@ typedef enum {
}, \
.dma_burst_len = ETH_DMA_BURST_LEN_32, \
.intr_priority = 0, \
.mdc_freq_hz = 0, \
.emac_dataif_gpio = \
{ \
.rmii = \

12
components/esp_eth/src/mac/esp_eth_mac_esp.c
View File

@@ -71,6 +71,7 @@ typedef struct {
bool flow_ctrl_enabled; // indicates whether the user want to do flow control
bool do_flow_ctrl; // indicates whether we need to do software flow control
bool use_pll; // Only use (A/M)PLL in EMAC_DATA_INTERFACE_RMII && EMAC_CLK_OUT
int32_t mdc_freq_hz;
#ifdef CONFIG_PM_ENABLE
esp_pm_lock_handle_t pm_lock;
#endif
@@ -427,7 +428,14 @@ static esp_err_t emac_esp32_init(esp_eth_mac_t *mac)
}
ESP_GOTO_ON_FALSE(to < emac->sw_reset_timeout_ms / 10, ESP_ERR_TIMEOUT, err, TAG, "reset timeout");
/* set smi clock */
emac_hal_set_csr_clock_range(&emac->hal, esp_clk_apb_freq());
uint32_t csr_freq_hz;
soc_module_clk_t csr_clk_src = emac_ll_get_csr_clk_src();
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(csr_clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, &csr_freq_hz), err, TAG, "get CSR frequency failed");
if (emac->mdc_freq_hz <= 0) {
emac_hal_set_csr_clock_range(&emac->hal, csr_freq_hz);
} else {
emac_hal_find_set_closest_csr_clock_range(&emac->hal, emac->mdc_freq_hz, csr_freq_hz);
}
/* init mac registers by default */
emac_hal_init_mac_default(&emac->hal);
/* init dma registers with selected EMAC-DMA configuration */
@@ -698,6 +706,8 @@ esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config
emac->dma_burst_len = esp32_config->dma_burst_len;
emac->sw_reset_timeout_ms = config->sw_reset_timeout_ms;
emac->mdc_freq_hz = esp32_config->mdc_freq_hz;
emac->flow_control_high_water_mark = FLOW_CONTROL_HIGH_WATER_MARK;
emac->flow_control_low_water_mark = FLOW_CONTROL_LOW_WATER_MARK;
emac->parent.set_mediator = emac_esp32_set_mediator;