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Merge branch 'fix/spi_master_bit_trans_add_check_v5.5' into 'release/v5.5'

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fix(driver_spi): spi master bit length check, dma internal align check and set idle level for all data pin (v5.5)

See merge request espressif/esp-idf!45134
This commit is contained in:
morris
2026-04-02 12:14:16 +08:00
parent c589856afe b519d672a8
commit c3a94d3084
20 changed files with 316 additions and 99 deletions
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components/hal/esp32s2/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -48,6 +48,8 @@ extern "C" {
#define SPI_LL_DMA_MAX_BIT_LEN (1 << 23) //reg len: 23 bits
#define SPI_LL_CPU_MAX_BIT_LEN (18 * 32) //Fifo len: 18 words
#define SPI_LL_TX_MINI_EXTRA_BITS 1 //Minimum length of TX non byte aligned data in bits
#define SPI_LL_RX_MINI_EXTRA_BITS 8 //Minimum length of RX non byte aligned data in bits
#define SPI_LL_MOSI_FREE_LEVEL 1 //Default level after bus initialized
#define SPI_LL_DMA_SHARED 1 //spi_dma shared with adc and dac on S2
@@ -263,13 +265,14 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
}
/**