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fix(riscv): implement a workaround for Zcmp hardware bug

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This commit is contained in:
Omar Chebib
2026-04-10 15:03:09 +08:00
parent add311ee4f
commit c27c33a832
8 changed files with 129 additions and 86 deletions
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components/riscv/vectors.S
+2 -2
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@@ -184,8 +184,8 @@
.macro mintthresh_csr_disable reg
#if __riscv_zcmp && SOC_CPU_ZCMP_WORKAROUND
/* Workaround for triggering an interrupt even when mstatus.mie is 0, when cm.push is called. */
li t0, 0xff
csrrw \reg, MINTTHRESH_CSR, t0
li \reg, 0xff
csrrw \reg, MINTTHRESH_CSR, \reg
#endif
.endm