Merge branch 'fix/i2s_tdm_5slot_clock_test_v6.0' into 'release/v6.0'

fix(hal): prevent overflow in fractional clock division (v6.0)

See merge request espressif/esp-idf!51430
This commit is contained in:
morris
2026-09-04 17:56:03 +08:00
2 changed files with 15 additions and 6 deletions
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -81,6 +81,14 @@ TEST_CASE("test_fractal_division", "[clk_div]")
TEST_ASSERT_EQUAL_UINT32(9, clk_div.integer);
TEST_ASSERT_UINT32_WITHIN(clk_info.exp_freq_hz * 0.0001, clk_info.exp_freq_hz, real_freq);
// Fractional division whose intermediate products exceed UINT32_MAX
clk_info.exp_freq_hz = 42 * 1000 * 1000 + 336 * 1000;
real_freq = hal_utils_calc_clk_div_frac_accurate(&clk_info, &clk_div);
TEST_ASSERT_EQUAL_UINT32(3, clk_div.integer);
TEST_ASSERT_EQUAL_UINT32(286, clk_div.numerator);
TEST_ASSERT_EQUAL_UINT32(367, clk_div.denominator);
TEST_ASSERT_EQUAL_UINT32(42335977, real_freq);
// Fractal division with no error
clk_info.exp_freq_hz = 50 * 1000 * 1000;
real_freq = hal_utils_calc_clk_div_frac_fast(&clk_info, &clk_div);