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panic on RISC-V: Take into account Merge Request comments

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This commit is contained in:
Omar Chebib
2020-12-31 15:46:17 +08:00
parent 5962b1dc56
commit c218f669ba
8 changed files with 38 additions and 41 deletions
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components/esp_system/port/arch/riscv/panic_arch.c
+6 -2
View File
@@ -184,11 +184,13 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
RvExcFrame *frame = (RvExcFrame *) f;
/* Please keep in sync with PANIC_RSN_* defines */
static const char *pseudo_reason[PANIC_RSN_MAX + 1] = {
static const char *pseudo_reason[PANIC_RSN_COUNT] = {
"Unknown reason",
"Interrupt wdt timeout on CPU0",
#if SOC_CPU_NUM > 1
"Interrupt wdt timeout on CPU1",
"Cache exception",
#endif
"Cache error"
};
info->reason = pseudo_reason[0];
@@ -213,8 +215,10 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
info->core = core;
info->exception = PANIC_EXCEPTION_TWDT;
#if SOC_CPU_NUM > 1
_Static_assert(PANIC_RSN_INTWDT_CPU0 + 1 == PANIC_RSN_INTWDT_CPU1,
"PANIC_RSN_INTWDT_CPU1 must be equal to PANIC_RSN_INTWDT_CPU0 + 1");
#endif
info->reason = pseudo_reason[PANIC_RSN_INTWDT_CPU0 + core];
}
}
components/esp_system/port/arch/xtensa/panic_arch.c
+1 -1
View File
@@ -411,7 +411,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
#if CONFIG_IDF_TARGET_ESP32
"Cache disabled but cached memory region accessed",
#elif CONFIG_IDF_TARGET_ESP32S2
"Cache exception",
"Cache error",
#endif
};