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Merge branch 'feature/esp32c3_uart_add_wakeup_event' into 'master'

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UART: add uart wakeup event for esp32c3 and esp32s3

Closes IDF-3416

See merge request espressif/esp-idf!14482
This commit is contained in:
Michael (XIAO Xufeng)
2022-02-04 17:23:29 +00:00
parent 93106c9348 c4cfb654d2
commit c1b30491dd
27 changed files with 413 additions and 159 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+4
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@@ -467,6 +467,10 @@ config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
+1 -1
View File
@@ -250,7 +250,7 @@
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -591,6 +591,10 @@ config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_REQUIRE_CORE_RESET
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
+1
View File
@@ -290,6 +290,7 @@
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_REQUIRE_CORE_RESET (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -563,6 +563,10 @@ config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+1 -1
View File
@@ -281,7 +281,7 @@
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_RTC_CLK (1)
#define SOC_UART_SUPPORT_XTAL_CLK (1)
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -583,6 +583,10 @@ config SOC_UART_NUM
int
default 2
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_SUPPORT_REF_TICK
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
+1
View File
@@ -277,6 +277,7 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-S2 has 2 UART.
#define SOC_UART_NUM (2)
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+20 -16
View File
@@ -667,6 +667,26 @@ config SOC_TOUCH_PAD_MEASURE_WAIT_MAX
hex
default 0xFF
config SOC_UART_NUM
int
default 3
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
@@ -846,19 +866,3 @@ config SOC_TWAI_BRP_MAX
config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_NUM
int
default 3
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
+7 -2
View File
@@ -264,8 +264,13 @@
#include "twai_caps.h"
/*-------------------------- UART CAPS ---------------------------------------*/
#include "uart_caps.h"
// ESP32-S3 has 3 UARTs
#define SOC_UART_NUM (3)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
components/soc/esp32s3/include/soc/uart_caps.h
-31
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@@ -1,31 +0,0 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_NUM (3)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#ifdef __cplusplus
}
#endif