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Merge branch 'fix/p4_fixed_mdc_config_v5.5' into 'release/v5.5'

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fix(esp_eth): fixed ESP32P4 CSR clock range used to determine MDC (v5.5)

See merge request espressif/esp-idf!44225
This commit is contained in:
Jiang Jiang Jian
2026-01-16 14:33:02 +08:00
parent f32cadd971 2a5b04b0b4
commit c1a09f9cef
10 changed files with 74 additions and 4 deletions
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components/hal/include/hal/clk_tree_hal.h
+9 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -35,7 +35,14 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src);
uint32_t clk_hal_cpu_get_freq_hz(void);
/**
* @brief Get APB_CLK frequency
* @brief Get SYS_CLK frequency, derived from MEM_CLK
*
* @return SYS clock frequency, in Hz. Returns 0 if internal clock configuration is invalid.
*/
uint32_t clk_hal_sys_get_freq_hz(void);
/**
* @brief Get APB_CLK frequency, derived from SYS_CLK
*
* @return APB clock frequency, in Hz. Returns 0 if internal clock configuration is invalid.
*/
components/hal/include/hal/emac_hal.h
+2
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@@ -246,6 +246,8 @@ void emac_hal_init(emac_hal_context_t *hal);
#define emac_hal_is_reset_done(hal) emac_ll_is_reset_done((hal)->dma_regs)
void emac_hal_find_set_closest_csr_clock_range(emac_hal_context_t *hal, int mdc_freq_hz, int freq_hz);
void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq);
void emac_hal_init_mac_default(emac_hal_context_t *hal);