Merge branch 'fix/p4_fixed_mdc_config_v5.5' into 'release/v5.5'

fix(esp_eth): fixed ESP32P4 CSR clock range used to determine MDC (v5.5)

See merge request espressif/esp-idf!44225

components/hal/esp32p4/clk_tree_hal.c

@@ -45,7 +45,7 @@ static uint32_t clk_hal_mem_get_freq_hz(void)
     return clk_hal_cpu_get_freq_hz() / clk_ll_mem_get_divider();
 }
 
-static uint32_t clk_hal_sys_get_freq_hz(void)
+uint32_t clk_hal_sys_get_freq_hz(void)
 {
     return clk_hal_mem_get_freq_hz() / clk_ll_sys_get_divider();
 }

components/hal/esp32p4/include/hal/emac_ll.h

@@ -816,6 +816,12 @@ static inline void emac_ll_ts_target_int_trig_enable(emac_ptp_dev_t *ptp_regs)
 
 /************** End of ptp regs operation ********************/
 
+static inline soc_module_clk_t emac_ll_get_csr_clk_src(void)
+{
+    // Source of the ESP32P4 EMAC CRS clock is SYS clock.
+    return SOC_MOD_CLK_SYS;
+}
+
 /**
  * @brief Enable the bus clock for the EMAC module
  *