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change(esp_hw_support): support esp32h21eco1 sleep flow

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hebinglin
2026-03-25 15:38:49 +08:00
parent 8ce11e1608
commit c09aaa64bf
13 changed files with 143 additions and 95 deletions
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components/esp_hal_pmu/esp32h4/include/hal/pmu_ll.h
+22 -1
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@@ -259,7 +259,7 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_power_detect_bypass(pmu_dev_t *hw
hw->hp_sys[mode].regulator0.power_det_bypass = bypass;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool dbias_sel)
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_select(pmu_dev_t *hw, pmu_hp_mode_t mode, bool dbias_sel)
{
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
hw->hp_sys[mode].regulator0.dbias_sel = dbias_sel;
@@ -843,6 +843,27 @@ FORCE_INLINE_ATTR void pmu_ll_set_dcdc_ccm_sw_en(pmu_dev_t *hw, bool en)
hw->dcm_ctrl.dcdc_ccm_sw_en = en;
}
FORCE_INLINE_ATTR void pmu_ll_set_ble_bandgap_ext_ocode(pmu_dev_t *hw, uint32_t ocode)
{
/* Field is 8 bits (see PMU_EXT_OCODE); mask matches REG_SET_FIELD(..., PMU_EXT_OCODE, x). */
hw->ble_bandgap_ctrl.ext_ocode = ocode & 0xFFU;
}
FORCE_INLINE_ATTR uint32_t pmu_ll_get_ble_bandgap_ext_ocode(pmu_dev_t *hw)
{
return hw->ble_bandgap_ctrl.ext_ocode;
}
FORCE_INLINE_ATTR void pmu_ll_set_ble_bandgap_ext_force_ocode(pmu_dev_t *hw, bool force)
{
hw->ble_bandgap_ctrl.ext_force_ocode = force;
}
FORCE_INLINE_ATTR bool pmu_ll_get_ble_bandgap_ext_force_ocode(pmu_dev_t *hw)
{
return hw->ble_bandgap_ctrl.ext_force_ocode;
}
#ifdef __cplusplus
}
#endif