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synced 2026-10-02 03:00:34 +03:00
change(esp_hw_support): support esp32h21eco1 sleep flow
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@@ -134,6 +134,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode,
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hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_xtalx2_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtalx2)
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{
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hw->hp_sys[mode].xtal.xpd_xtalx2 = xpd_xtalx2;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_discnnt_dig_rtc(pmu_dev_t *hw, pmu_hp_mode_t mode, bool discnnt)
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{
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hw->hp_sys[mode].bias.discnnt_dig_rtc = discnnt;
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@@ -299,6 +304,12 @@ FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode,
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hw->lp_sys[mode].xtal.xpd_xtal = slp_xpd;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_set_xtalx2_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtalx2)
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{
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HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
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hw->lp_sys[mode].xtal.xpd_xtalx2 = xpd_xtalx2;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
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{
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hw->lp_sys[mode].dig_power.val = flag;
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@@ -320,6 +331,12 @@ FORCE_INLINE_ATTR void pmu_ll_lp_set_dcdc_ccm_enable(pmu_dev_t *hw, pmu_lp_mode_
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hw->lp_sys[mode].bias.dcdc_ccm_enb = enable;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_set_dcdc_clear_ready(pmu_dev_t *hw, pmu_lp_mode_t mode, bool clear_rdy)
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{
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HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
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hw->lp_sys[mode].bias.dcdc_clear_rdy = clear_rdy;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_reg_dpcur_bias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
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{
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HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
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@@ -764,7 +781,8 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_get_dcdc_boost_dreg(pmu_dev_t *hw)
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FORCE_INLINE_ATTR void pmu_ll_set_ble_bandgap_ext_ocode(pmu_dev_t *hw, uint32_t ocode)
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{
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hw->ble_bandgap_ctrl.ext_ocode = ocode;
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/* Field is 8 bits (see PMU_EXT_OCODE); mask matches REG_SET_FIELD(..., PMU_EXT_OCODE, x). */
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hw->ble_bandgap_ctrl.ext_ocode = ocode & 0xFFU;
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}
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FORCE_INLINE_ATTR uint32_t pmu_ll_get_ble_bandgap_ext_ocode(pmu_dev_t *hw)
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