mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 11:10:54 +03:00
fix(drivers): fix typos found by codespell
codespell components/esp_driver*
This commit is contained in:
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -659,7 +659,7 @@ TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)"
|
||||
TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi));
|
||||
|
||||
printf("before second xmit\n");
|
||||
// the original version (bit mis-written) stucks here.
|
||||
// the original version (bit miswritten) stucks here.
|
||||
TEST_ESP_OK(spi_device_transmit(spi, &transaction));
|
||||
// test case success when see this.
|
||||
printf("after second xmit\n");
|
||||
@@ -874,7 +874,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
addr_bits = 56 - 8 * i;
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
||||
//ESP32S2 only supportes up to 32 bits address
|
||||
//ESP32S2 only supports up to 32 bits address
|
||||
addr_bits = 28 - 4 * i;
|
||||
#endif
|
||||
int round_up = (cmd_bits + addr_bits + 7) / 8 * 8;
|
||||
@@ -1529,7 +1529,7 @@ void test_add_device_master(void)
|
||||
//1. add max dummy devices
|
||||
//2. replace devs[i] as a real device, than start a transaction
|
||||
//3. free devs[i] after transaction to release the real CS pin for using again by another dev,
|
||||
//So it will loop to check every gpio_sigal one by one use one physical pin
|
||||
//So it will loop to check every gpio_signal one by one use one physical pin
|
||||
spi_bus_remove_device(devs[i]);
|
||||
dev_cfg.spics_io_num = CS_REAL_DEV;
|
||||
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i]));
|
||||
@@ -1608,7 +1608,7 @@ TEST_CASE("test_master_isr_pin_to_core", "[spi]")
|
||||
{
|
||||
spi_device_handle_t dev0;
|
||||
uint32_t master_send;
|
||||
uint32_t master_recive;
|
||||
uint32_t master_receive;
|
||||
uint32_t master_expect;
|
||||
|
||||
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
|
||||
@@ -1617,7 +1617,7 @@ TEST_CASE("test_master_isr_pin_to_core", "[spi]")
|
||||
|
||||
spi_transaction_t trans_cfg = {
|
||||
.tx_buffer = &master_send,
|
||||
.rx_buffer = &master_recive,
|
||||
.rx_buffer = &master_receive,
|
||||
.user = & master_expect,
|
||||
.length = sizeof(uint32_t) * 8,
|
||||
};
|
||||
@@ -1684,7 +1684,7 @@ static IRAM_ATTR void test_master_iram(void)
|
||||
.length = TEST_MASTER_IRAM_TRANS_LEN * 8,
|
||||
}, *ret_trans;
|
||||
|
||||
// Test intrrupt trans api once -----------------------------
|
||||
// Test interrupt trans api once -----------------------------
|
||||
unity_send_signal("Master ready");
|
||||
unity_wait_for_signal("Slave ready");
|
||||
|
||||
@@ -1692,7 +1692,7 @@ static IRAM_ATTR void test_master_iram(void)
|
||||
flag_trans_done = false;
|
||||
spi_device_queue_trans(dev_handle, &trans_cfg, portMAX_DELAY);
|
||||
while (!flag_trans_done) {
|
||||
// waitting for transaction done and return from ISR
|
||||
// waiting for transaction done and return from ISR
|
||||
}
|
||||
spi_device_get_trans_result(dev_handle, &ret_trans, portMAX_DELAY);
|
||||
spi_flash_enable_interrupts_caches_and_other_cpu();
|
||||
|
||||
@@ -76,7 +76,7 @@ static void hd_master(void)
|
||||
.tx_buffer = (uint8_t *) &master_tx_val,
|
||||
},
|
||||
},
|
||||
//TEST_HD_DATA_LEN of TX data, splitted into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
|
||||
//TEST_HD_DATA_LEN of TX data, split into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
|
||||
{
|
||||
.base = {
|
||||
.cmd = 0x3,
|
||||
@@ -120,7 +120,7 @@ static void hd_master(void)
|
||||
.rx_buffer = (uint8_t *) &master_rx_val,
|
||||
},
|
||||
},
|
||||
// TEST_HD_DATA_LEN of TX data, splitted into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
|
||||
// TEST_HD_DATA_LEN of TX data, split into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
|
||||
{
|
||||
.base = {
|
||||
.cmd = 0x4,
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -143,8 +143,8 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]")
|
||||
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) //IDF-7503 slave support
|
||||
/********************************************************************************
|
||||
* Test SIO Master
|
||||
* SIO Slave is not suported, and one unit test is limited to one feature, so,,,
|
||||
* sio master test can be splited to singal-input and single-output
|
||||
* SIO Slave is not supported, and one unit test is limited to one feature, so,,,
|
||||
* sio master test can be split to signal-input and single-output
|
||||
*
|
||||
* for single-output: master slave
|
||||
* cs-----cs ------------- cs
|
||||
@@ -178,7 +178,7 @@ void test_sio_master_trans(bool sio_master_in)
|
||||
uint8_t *master_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
|
||||
TEST_ASSERT_NOT_NULL_MESSAGE(master_tx_max, "malloc failed, exit.\n");
|
||||
|
||||
// write somethin to a long buffer for test long transmition
|
||||
// write somethin to a long buffer for test long transmission
|
||||
for (uint16_t i = 0; i < TRANS_LEN; i++) {
|
||||
master_tx_max[i] = i;
|
||||
master_tx_max[TRANS_LEN * 2 - i - 1] = i;
|
||||
@@ -208,7 +208,7 @@ void test_sio_master_trans(bool sio_master_in)
|
||||
if (sio_master_in) {
|
||||
// master input only section
|
||||
trans.rxlength = (i + 1) * 8 * 8;
|
||||
// test a huge data for last transmition
|
||||
// test a huge data for last transmission
|
||||
if (i >= TEST_NUM - 1) {
|
||||
trans.rxlength = TRANS_LEN * 8;
|
||||
}
|
||||
@@ -219,14 +219,14 @@ void test_sio_master_trans(bool sio_master_in)
|
||||
} else {
|
||||
// master output only section
|
||||
trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
|
||||
// test a huge data for last transmition
|
||||
// test a huge data for last transmission
|
||||
if (i >= TEST_NUM - 1) {
|
||||
trans.length = TRANS_LEN * 8;
|
||||
}
|
||||
trans.tx_buffer = master_tx_max;
|
||||
trans.rxlength = 0;
|
||||
trans.rx_buffer = NULL;
|
||||
// use some differnt data
|
||||
// use some different data
|
||||
trans.tx_buffer += (i % 2) ? TRANS_LEN : 0;
|
||||
}
|
||||
|
||||
@@ -252,7 +252,7 @@ void test_sio_slave_emulate(bool sio_master_in)
|
||||
uint8_t *slave_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
|
||||
TEST_ASSERT_NOT_NULL_MESSAGE(slave_tx_max, "malloc failed, exit.\n");
|
||||
|
||||
// write somethin to a long buffer for test long transmition
|
||||
// write somethin to a long buffer for test long transmission
|
||||
for (uint16_t i = 0; i < TRANS_LEN; i++) {
|
||||
slave_tx_max[i] = i;
|
||||
slave_tx_max[TRANS_LEN * 2 - i - 1] = i;
|
||||
@@ -275,7 +275,7 @@ void test_sio_slave_emulate(bool sio_master_in)
|
||||
if (sio_master_in) {
|
||||
// slave output only section
|
||||
trans.length = (i + 1) * 8 * 8;
|
||||
// test a huge data for last transmition
|
||||
// test a huge data for last transmission
|
||||
if (i >= TEST_NUM - 1) {
|
||||
trans.length = TRANS_LEN * 8;
|
||||
}
|
||||
@@ -284,7 +284,7 @@ void test_sio_slave_emulate(bool sio_master_in)
|
||||
} else {
|
||||
// slave input only section
|
||||
trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
|
||||
// test a huge data for last transmition
|
||||
// test a huge data for last transmission
|
||||
if (i >= TEST_NUM - 1) {
|
||||
trans.length = TRANS_LEN * 8;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user