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fix(drivers): fix typos found by codespell

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codespell components/esp_driver*
This commit is contained in:
morris
2024-03-28 10:01:27 +08:00
parent 2ee266c0d6
commit c0289ee6eb
131 changed files with 327 additions and 327 deletions
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components/esp_driver_spi/test_apps/master/main/test_spi_master.c
+8 -8
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -659,7 +659,7 @@ TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)"
TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi));
printf("before second xmit\n");
// the original version (bit mis-written) stucks here.
// the original version (bit miswritten) stucks here.
TEST_ESP_OK(spi_device_transmit(spi, &transaction));
// test case success when see this.
printf("after second xmit\n");
@@ -874,7 +874,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
#ifdef CONFIG_IDF_TARGET_ESP32
addr_bits = 56 - 8 * i;
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
//ESP32S2 only supportes up to 32 bits address
//ESP32S2 only supports up to 32 bits address
addr_bits = 28 - 4 * i;
#endif
int round_up = (cmd_bits + addr_bits + 7) / 8 * 8;
@@ -1529,7 +1529,7 @@ void test_add_device_master(void)
//1. add max dummy devices
//2. replace devs[i] as a real device, than start a transaction
//3. free devs[i] after transaction to release the real CS pin for using again by another dev,
//So it will loop to check every gpio_sigal one by one use one physical pin
//So it will loop to check every gpio_signal one by one use one physical pin
spi_bus_remove_device(devs[i]);
dev_cfg.spics_io_num = CS_REAL_DEV;
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &devs[i]));
@@ -1608,7 +1608,7 @@ TEST_CASE("test_master_isr_pin_to_core", "[spi]")
{
spi_device_handle_t dev0;
uint32_t master_send;
uint32_t master_recive;
uint32_t master_receive;
uint32_t master_expect;
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
@@ -1617,7 +1617,7 @@ TEST_CASE("test_master_isr_pin_to_core", "[spi]")
spi_transaction_t trans_cfg = {
.tx_buffer = &master_send,
.rx_buffer = &master_recive,
.rx_buffer = &master_receive,
.user = & master_expect,
.length = sizeof(uint32_t) * 8,
};
@@ -1684,7 +1684,7 @@ static IRAM_ATTR void test_master_iram(void)
.length = TEST_MASTER_IRAM_TRANS_LEN * 8,
}, *ret_trans;
// Test intrrupt trans api once -----------------------------
// Test interrupt trans api once -----------------------------
unity_send_signal("Master ready");
unity_wait_for_signal("Slave ready");
@@ -1692,7 +1692,7 @@ static IRAM_ATTR void test_master_iram(void)
flag_trans_done = false;
spi_device_queue_trans(dev_handle, &trans_cfg, portMAX_DELAY);
while (!flag_trans_done) {
// waitting for transaction done and return from ISR
// waiting for transaction done and return from ISR
}
spi_device_get_trans_result(dev_handle, &ret_trans, portMAX_DELAY);
spi_flash_enable_interrupts_caches_and_other_cpu();
components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c
+2 -2
View File
@@ -76,7 +76,7 @@ static void hd_master(void)
.tx_buffer = (uint8_t *) &master_tx_val,
},
},
//TEST_HD_DATA_LEN of TX data, splitted into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
//TEST_HD_DATA_LEN of TX data, split into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
{
.base = {
.cmd = 0x3,
@@ -120,7 +120,7 @@ static void hd_master(void)
.rx_buffer = (uint8_t *) &master_rx_val,
},
},
// TEST_HD_DATA_LEN of TX data, splitted into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
// TEST_HD_DATA_LEN of TX data, split into 2 segments. `TEST_HD_DATA_LEN_PER_SEG` per segment
{
.base = {
.cmd = 0x4,
components/esp_driver_spi/test_apps/master/main/test_spi_sio.c
+10 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -143,8 +143,8 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]")
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) //IDF-7503 slave support
/********************************************************************************
* Test SIO Master
* SIO Slave is not suported, and one unit test is limited to one feature, so,,,
* sio master test can be splited to singal-input and single-output
* SIO Slave is not supported, and one unit test is limited to one feature, so,,,
* sio master test can be split to signal-input and single-output
*
* for single-output: master slave
* cs-----cs ------------- cs
@@ -178,7 +178,7 @@ void test_sio_master_trans(bool sio_master_in)
uint8_t *master_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
TEST_ASSERT_NOT_NULL_MESSAGE(master_tx_max, "malloc failed, exit.\n");
// write somethin to a long buffer for test long transmition
// write somethin to a long buffer for test long transmission
for (uint16_t i = 0; i < TRANS_LEN; i++) {
master_tx_max[i] = i;
master_tx_max[TRANS_LEN * 2 - i - 1] = i;
@@ -208,7 +208,7 @@ void test_sio_master_trans(bool sio_master_in)
if (sio_master_in) {
// master input only section
trans.rxlength = (i + 1) * 8 * 8;
// test a huge data for last transmition
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.rxlength = TRANS_LEN * 8;
}
@@ -219,14 +219,14 @@ void test_sio_master_trans(bool sio_master_in)
} else {
// master output only section
trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
// test a huge data for last transmition
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.length = TRANS_LEN * 8;
}
trans.tx_buffer = master_tx_max;
trans.rxlength = 0;
trans.rx_buffer = NULL;
// use some differnt data
// use some different data
trans.tx_buffer += (i % 2) ? TRANS_LEN : 0;
}
@@ -252,7 +252,7 @@ void test_sio_slave_emulate(bool sio_master_in)
uint8_t *slave_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
TEST_ASSERT_NOT_NULL_MESSAGE(slave_tx_max, "malloc failed, exit.\n");
// write somethin to a long buffer for test long transmition
// write somethin to a long buffer for test long transmission
for (uint16_t i = 0; i < TRANS_LEN; i++) {
slave_tx_max[i] = i;
slave_tx_max[TRANS_LEN * 2 - i - 1] = i;
@@ -275,7 +275,7 @@ void test_sio_slave_emulate(bool sio_master_in)
if (sio_master_in) {
// slave output only section
trans.length = (i + 1) * 8 * 8;
// test a huge data for last transmition
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.length = TRANS_LEN * 8;
}
@@ -284,7 +284,7 @@ void test_sio_slave_emulate(bool sio_master_in)
} else {
// slave input only section
trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
// test a huge data for last transmition
// test a huge data for last transmission
if (i >= TEST_NUM - 1) {
trans.length = TRANS_LEN * 8;
}
components/esp_driver_spi/test_apps/param/main/test_spi_param.c
+73 -73
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1284,7 +1284,7 @@ static void test_master_fd_dma(void)
{
spi_device_handle_t dev0;
uint8_t *master_send = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_recive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_receive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_expect = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1314,22 +1314,22 @@ static void test_master_fd_dma(void)
unity_send_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(master_recive, 0x00, TEST_STEP_LEN);
memset(master_receive, 0x00, TEST_STEP_LEN);
test_fill_random_to_buffers_dualboard(119 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN);
uint32_t test_trans_len = TEST_STEP_LEN;
spi_transaction_t trans_cfg = {
.tx_buffer = master_send,
.rx_buffer = master_recive,
.rx_buffer = master_receive,
.length = test_trans_len * 8,
};
unity_wait_for_signal("Slave ready");
TEST_ESP_OK(spi_device_transmit(dev0, &trans_cfg));
ESP_LOG_BUFFER_HEX("master tx", master_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master exp", master_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(master_expect, master_recive, test_trans_len);
spitest_cmp_or_dump(master_expect, master_receive, test_trans_len);
}
TEST_ESP_OK(spi_bus_remove_device(dev0));
}
@@ -1337,14 +1337,14 @@ static void test_master_fd_dma(void)
}
}
free(master_send);
free(master_recive);
free(master_receive);
free(master_expect);
}
static void test_slave_fd_dma(void)
{
uint8_t *slave_send = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_recive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_receive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_expect = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1365,13 +1365,13 @@ static void test_slave_fd_dma(void)
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (is_gpio) ? "GPIO_Matrix" : "IOMUX", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_wait_for_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(slave_recive, 0x00, TEST_STEP_LEN);
memset(slave_receive, 0x00, TEST_STEP_LEN);
test_fill_random_to_buffers_dualboard(119 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN);
uint32_t test_trans_len = TEST_STEP_LEN;
spi_slave_transaction_t trans_cfg = {
.tx_buffer = slave_send,
.rx_buffer = slave_recive,
.rx_buffer = slave_receive,
.length = test_trans_len * 8,
.flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
};
@@ -1379,16 +1379,16 @@ static void test_slave_fd_dma(void)
TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY));
ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave exp", slave_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(slave_expect, slave_recive, test_trans_len);
spitest_cmp_or_dump(slave_expect, slave_receive, test_trans_len);
}
}
TEST_ESP_OK(spi_slave_free(TEST_SPI_HOST));
}
}
free(slave_send);
free(slave_recive);
free(slave_receive);
free(slave_expect);
}
@@ -1399,7 +1399,7 @@ static void test_master_fd_no_dma(void)
{
spi_device_handle_t dev0;
uint8_t *master_send = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_recive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_receive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_expect = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1429,22 +1429,22 @@ static void test_master_fd_no_dma(void)
unity_send_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(master_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
memset(master_receive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
test_fill_random_to_buffers_dualboard(211 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE);
uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE;
spi_transaction_t trans_cfg = {
.tx_buffer = master_send,
.rx_buffer = master_recive,
.rx_buffer = master_receive,
.length = test_trans_len * 8,
};
unity_wait_for_signal("Slave ready");
TEST_ESP_OK(spi_device_transmit(dev0, &trans_cfg));
ESP_LOG_BUFFER_HEX("master tx", master_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master exp", master_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(master_expect, master_recive, test_trans_len);
spitest_cmp_or_dump(master_expect, master_receive, test_trans_len);
}
TEST_ESP_OK(spi_bus_remove_device(dev0));
}
@@ -1452,14 +1452,14 @@ static void test_master_fd_no_dma(void)
}
}
free(master_send);
free(master_recive);
free(master_receive);
free(master_expect);
}
static void test_slave_fd_no_dma(void)
{
uint8_t *slave_send = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_recive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_receive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_expect = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1481,29 +1481,29 @@ static void test_slave_fd_no_dma(void)
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (is_gpio) ? "GPIO_Matrix" : "IOMUX", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_wait_for_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(slave_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
memset(slave_receive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
test_fill_random_to_buffers_dualboard(211 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE);
uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE;
spi_slave_transaction_t trans_cfg = {
.tx_buffer = slave_send,
.rx_buffer = slave_recive,
.rx_buffer = slave_receive,
.length = test_trans_len * 8,
};
unity_send_signal("Slave ready");
TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY));
ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave exp", slave_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(slave_expect, slave_recive, test_trans_len);
spitest_cmp_or_dump(slave_expect, slave_receive, test_trans_len);
}
}
TEST_ESP_OK(spi_slave_free(TEST_SPI_HOST));
}
}
free(slave_send);
free(slave_recive);
free(slave_receive);
free(slave_expect);
}
@@ -1515,7 +1515,7 @@ static void test_master_hd_dma(void)
{
spi_device_handle_t dev0;
uint8_t *master_send = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_recive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_receive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_expect = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1536,18 +1536,18 @@ static void test_master_hd_dma(void)
unity_send_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(master_recive, 0x00, TEST_STEP_LEN);
memset(master_receive, 0x00, TEST_STEP_LEN);
test_fill_random_to_buffers_dualboard(985 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN);
uint32_t test_trans_len = TEST_STEP_LEN;
unity_wait_for_signal("Slave ready");
TEST_ESP_OK(essl_spi_rddma(dev0, master_recive, test_trans_len, -1, 0));
TEST_ESP_OK(essl_spi_rddma(dev0, master_receive, test_trans_len, -1, 0));
TEST_ESP_OK(essl_spi_wrdma(dev0, master_send, test_trans_len, -1, 0));
ESP_LOG_BUFFER_HEX("master tx", master_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master exp", master_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(master_expect, master_recive, test_trans_len);
spitest_cmp_or_dump(master_expect, master_receive, test_trans_len);
}
TEST_ESP_OK(spi_bus_remove_device(dev0));
}
@@ -1555,14 +1555,14 @@ static void test_master_hd_dma(void)
}
}
free(master_send);
free(master_recive);
free(master_receive);
free(master_expect);
}
static void test_slave_hd_dma(void)
{
uint8_t *slave_send = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_recive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_receive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_expect = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1580,7 +1580,7 @@ static void test_slave_hd_dma(void)
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (is_gpio) ? "GPIO_Matrix" : "IOMUX", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_wait_for_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(slave_recive, 0x00, TEST_STEP_LEN);
memset(slave_receive, 0x00, TEST_STEP_LEN);
test_fill_random_to_buffers_dualboard(985 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN);
uint32_t test_trans_len = TEST_STEP_LEN;
@@ -1591,21 +1591,21 @@ static void test_slave_hd_dma(void)
};
unity_send_signal("Slave ready");
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_trans, portMAX_DELAY));
slave_trans.data = slave_recive;
slave_trans.data = slave_receive;
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_trans, portMAX_DELAY));
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave exp", slave_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(slave_expect, slave_recive, test_trans_len);
spitest_cmp_or_dump(slave_expect, slave_receive, test_trans_len);
}
}
TEST_ESP_OK(spi_slave_hd_deinit(TEST_SPI_HOST));
}
}
free(slave_send);
free(slave_recive);
free(slave_receive);
free(slave_expect);
}
@@ -1616,7 +1616,7 @@ static void test_master_hd_no_dma(void)
{
spi_device_handle_t dev0;
uint8_t *master_send = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_recive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_receive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_expect = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1637,18 +1637,18 @@ static void test_master_hd_no_dma(void)
unity_send_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(master_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
memset(master_receive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
test_fill_random_to_buffers_dualboard(911 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE);
uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE;
unity_wait_for_signal("Slave ready");
TEST_ESP_OK(essl_spi_rddma(dev0, master_recive, test_trans_len, -1, 0));
TEST_ESP_OK(essl_spi_rddma(dev0, master_receive, test_trans_len, -1, 0));
TEST_ESP_OK(essl_spi_wrdma(dev0, master_send, test_trans_len, -1, 0));
ESP_LOG_BUFFER_HEX("master tx", master_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master exp", master_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(master_expect, master_recive, test_trans_len);
spitest_cmp_or_dump(master_expect, master_receive, test_trans_len);
}
TEST_ESP_OK(spi_bus_remove_device(dev0));
}
@@ -1656,14 +1656,14 @@ static void test_master_hd_no_dma(void)
}
}
free(master_send);
free(master_recive);
free(master_receive);
free(master_expect);
}
static void test_slave_hd_no_dma(void)
{
uint8_t *slave_send = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_recive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_receive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_expect = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DEFAULT);
for (uint8_t is_gpio = 0; is_gpio < 2; is_gpio++) {
@@ -1681,7 +1681,7 @@ static void test_slave_hd_no_dma(void)
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (is_gpio) ? "GPIO_Matrix" : "IOMUX", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_wait_for_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(slave_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
memset(slave_receive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
test_fill_random_to_buffers_dualboard(911 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE);
uint32_t test_trans_len = SOC_SPI_MAXIMUM_BUFFER_SIZE;
@@ -1692,21 +1692,21 @@ static void test_slave_hd_no_dma(void)
};
unity_send_signal("Slave ready");
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_trans, portMAX_DELAY));
slave_trans.data = slave_recive;
slave_trans.data = slave_receive;
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_trans, portMAX_DELAY));
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_recive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave rx", slave_receive, test_trans_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("slave exp", slave_expect, test_trans_len, ESP_LOG_DEBUG);
spitest_cmp_or_dump(slave_expect, slave_recive, test_trans_len);
spitest_cmp_or_dump(slave_expect, slave_receive, test_trans_len);
}
}
TEST_ESP_OK(spi_slave_hd_deinit(TEST_SPI_HOST));
}
}
free(slave_send);
free(slave_recive);
free(slave_receive);
free(slave_expect);
}
@@ -1722,7 +1722,7 @@ static void test_master_sio_dma(void)
{
spi_device_handle_t dev0;
uint8_t *master_send = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_recive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_receive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *master_expect = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DEFAULT);
for (uint8_t sio_master_in = 0; sio_master_in < 2; sio_master_in++) {
@@ -1752,17 +1752,17 @@ static void test_master_sio_dma(void)
devcfg.input_delay_ns = s_master_input_delay[speed_level];
#endif
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &dev0));
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SongleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SingleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_send_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(master_recive, 0x00, TEST_STEP_LEN);
memset(master_receive, 0x00, TEST_STEP_LEN);
test_fill_random_to_buffers_dualboard(110 + mode + speed_level + i, master_send, master_expect, TEST_STEP_LEN);
spi_transaction_t trans = {};
if (sio_master_in) {
// master input only
trans.rxlength = TEST_STEP_LEN * 8;
trans.rx_buffer = master_recive;
trans.rx_buffer = master_receive;
trans.length = 0;
trans.tx_buffer = NULL;
} else {
@@ -1778,7 +1778,7 @@ static void test_master_sio_dma(void)
if (sio_master_in) {
ESP_LOG_BUFFER_HEX_LEVEL("master rx", trans.rx_buffer, TEST_STEP_LEN, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master exp", master_expect, TEST_STEP_LEN, ESP_LOG_DEBUG);
spitest_cmp_or_dump(master_expect, master_recive, TEST_STEP_LEN);
spitest_cmp_or_dump(master_expect, master_receive, TEST_STEP_LEN);
} else {
ESP_LOG_BUFFER_HEX("master tx", trans.tx_buffer, TEST_STEP_LEN);
}
@@ -1789,14 +1789,14 @@ static void test_master_sio_dma(void)
}
}
free(master_send);
free(master_recive);
free(master_receive);
free(master_expect);
}
static void test_slave_sio_dma(void)
{
uint8_t *slave_send = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_recive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_receive = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DMA);
uint8_t *slave_expect = heap_caps_malloc(TEST_STEP_LEN, MALLOC_CAP_DEFAULT);
for (uint8_t sio_master_in = 0; sio_master_in < 2; sio_master_in++) {
@@ -1814,16 +1814,16 @@ static void test_slave_sio_dma(void)
slv_cfg.mode = mode;
TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &bus_cfg, &slv_cfg, SPI_DMA_CH_AUTO));
for (uint8_t speed_level = 0; speed_level < sizeof(s_spi_bus_freq) / sizeof(int); speed_level++) {
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SongleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SingleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_wait_for_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(slave_recive, 0x00, TEST_STEP_LEN);
memset(slave_receive, 0x00, TEST_STEP_LEN);
test_fill_random_to_buffers_dualboard(110 + mode + speed_level + i, slave_expect, slave_send, TEST_STEP_LEN);
spi_slave_transaction_t trans = {
.length = TEST_STEP_LEN * 8,
.tx_buffer = slave_send,
.rx_buffer = slave_recive,
.rx_buffer = slave_receive,
.flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
};
unity_send_signal("Slave ready");
@@ -1834,7 +1834,7 @@ static void test_slave_sio_dma(void)
} else {
ESP_LOG_BUFFER_HEX_LEVEL("Slave rx", trans.rx_buffer, TEST_STEP_LEN, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("Slave exp", slave_expect, TEST_STEP_LEN, ESP_LOG_DEBUG);
spitest_cmp_or_dump(slave_expect, slave_recive, TEST_STEP_LEN);
spitest_cmp_or_dump(slave_expect, slave_receive, TEST_STEP_LEN);
}
}
}
@@ -1842,7 +1842,7 @@ static void test_slave_sio_dma(void)
}
}
free(slave_send);
free(slave_recive);
free(slave_receive);
free(slave_expect);
}
@@ -1853,7 +1853,7 @@ static void test_master_sio_no_dma(void)
{
spi_device_handle_t dev0;
uint8_t *master_send = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_recive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_receive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *master_expect = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DEFAULT);
for (uint8_t sio_master_in = 0; sio_master_in < 2; sio_master_in++) {
@@ -1884,17 +1884,17 @@ static void test_master_sio_no_dma(void)
devcfg.input_delay_ns = s_master_input_delay[speed_level];
#endif
TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &dev0));
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SongleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SingleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_send_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(master_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
memset(master_receive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
test_fill_random_to_buffers_dualboard(122 + mode + speed_level + i, master_send, master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE);
spi_transaction_t trans = {};
if (sio_master_in) {
// master input only
trans.rxlength = SOC_SPI_MAXIMUM_BUFFER_SIZE * 8;
trans.rx_buffer = master_recive;
trans.rx_buffer = master_receive;
trans.length = 0;
trans.tx_buffer = NULL;
} else {
@@ -1910,7 +1910,7 @@ static void test_master_sio_no_dma(void)
if (sio_master_in) {
ESP_LOG_BUFFER_HEX_LEVEL("master rx", trans.rx_buffer, SOC_SPI_MAXIMUM_BUFFER_SIZE, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("master exp", master_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE, ESP_LOG_DEBUG);
spitest_cmp_or_dump(master_expect, master_recive, SOC_SPI_MAXIMUM_BUFFER_SIZE);
spitest_cmp_or_dump(master_expect, master_receive, SOC_SPI_MAXIMUM_BUFFER_SIZE);
} else {
ESP_LOG_BUFFER_HEX("master tx", trans.tx_buffer, SOC_SPI_MAXIMUM_BUFFER_SIZE);
}
@@ -1921,14 +1921,14 @@ static void test_master_sio_no_dma(void)
}
}
free(master_send);
free(master_recive);
free(master_receive);
free(master_expect);
}
static void test_slave_sio_no_dma(void)
{
uint8_t *slave_send = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_recive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_receive = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DMA);
uint8_t *slave_expect = heap_caps_malloc(SOC_SPI_MAXIMUM_BUFFER_SIZE, MALLOC_CAP_DEFAULT);
for (uint8_t sio_master_in = 0; sio_master_in < 2; sio_master_in++) {
@@ -1947,16 +1947,16 @@ static void test_slave_sio_no_dma(void)
TEST_ESP_OK(spi_slave_initialize(TEST_SPI_HOST, &bus_cfg, &slv_cfg, SPI_DMA_DISABLED));
for (uint8_t speed_level = 0; speed_level < sizeof(s_spi_bus_freq) / sizeof(int); speed_level++) {
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SongleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
printf("Next trans: %s\tmode:%d\t@%.2f MHz\n", (sio_master_in) ? "SingleIn" : "SingleOut", mode, s_spi_bus_freq[speed_level] / 1000000.f);
unity_wait_for_signal("Master ready");
for (int i = 0; i < TEST_STEP; i++) {
memset(slave_recive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
memset(slave_receive, 0x00, SOC_SPI_MAXIMUM_BUFFER_SIZE);
test_fill_random_to_buffers_dualboard(122 + mode + speed_level + i, slave_expect, slave_send, SOC_SPI_MAXIMUM_BUFFER_SIZE);
spi_slave_transaction_t trans = {
.length = SOC_SPI_MAXIMUM_BUFFER_SIZE * 8,
.tx_buffer = slave_send,
.rx_buffer = slave_recive,
.rx_buffer = slave_receive,
};
unity_send_signal("Slave ready");
TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans, portMAX_DELAY));
@@ -1966,7 +1966,7 @@ static void test_slave_sio_no_dma(void)
} else {
ESP_LOG_BUFFER_HEX_LEVEL("Slave rx", trans.rx_buffer, SOC_SPI_MAXIMUM_BUFFER_SIZE, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEX_LEVEL("Slave exp", slave_expect, SOC_SPI_MAXIMUM_BUFFER_SIZE, ESP_LOG_DEBUG);
spitest_cmp_or_dump(slave_expect, slave_recive, SOC_SPI_MAXIMUM_BUFFER_SIZE);
spitest_cmp_or_dump(slave_expect, slave_receive, SOC_SPI_MAXIMUM_BUFFER_SIZE);
}
}
}
@@ -1974,7 +1974,7 @@ static void test_slave_sio_no_dma(void)
}
}
free(slave_send);
free(slave_recive);
free(slave_receive);
free(slave_expect);
}
components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,7 +53,7 @@ static void master_init(spi_device_handle_t *spi)
.quadhd_io_num = -1
};
spi_device_interface_config_t devcfg = {
.clock_speed_hz = 4 * 1000 * 1000, //currently only up to 4MHz for internel connect
.clock_speed_hz = 4 * 1000 * 1000, //currently only up to 4MHz for internal connect
.mode = 0, //SPI mode 0
.spics_io_num = PIN_NUM_CS, //CS pin
.queue_size = 7, //We want to be able to queue 7 transactions at a time
@@ -703,7 +703,7 @@ static void test_slave_isr_core_setup_cbk(spi_slave_transaction_t *curr_trans)
TEST_CASE("test_slave_isr_pin_to_core", "[spi]")
{
uint32_t slave_send;
uint32_t slave_recive;
uint32_t slave_receive;
uint32_t slave_expect;
spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
@@ -712,7 +712,7 @@ TEST_CASE("test_slave_isr_pin_to_core", "[spi]")
spi_slave_transaction_t trans_cfg = {
.tx_buffer = &slave_send,
.rx_buffer = &slave_recive,
.rx_buffer = &slave_receive,
.user = &slave_expect,
.length = sizeof(uint32_t) * 8,
};
components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
+1 -1
View File
@@ -922,7 +922,7 @@ void prepare_data(uint8_t *buff, uint32_t len, int8_t diff)
void slave_run_append(void)
{
spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
bus_cfg.max_transfer_sz = 40000; //will prepare 40000/DMA_MAX_BUFF_SIZE +1 dma desciptor for use
bus_cfg.max_transfer_sz = 40000; //will prepare 40000/DMA_MAX_BUFF_SIZE +1 dma descriptor for use
spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG();
slave_hd_cfg.flags |= SPI_SLAVE_HD_APPEND_MODE;