fix(esp_rom): Patch the esp_rom_delay_us API to use U-mode cycle CSR

components/esp_rom/esp32c61/Kconfig.soc_caps.in

@@ -114,3 +114,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
 config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
     bool
     default y
+
+config ESP_ROM_DELAY_US_PATCH
+    bool
+    default y

components/esp_rom/esp32c61/esp_rom_caps.h

@@ -34,3 +34,4 @@
 #define ESP_ROM_USB_OTG_NUM                 (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
+#define ESP_ROM_DELAY_US_PATCH              (1) // ROM ets_delay_us needs patch for U-mode operation

components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h

@@ -64,9 +64,9 @@ struct ETSEventTag {
 typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processor*/
 typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
 
-
-
-
+typedef struct ets_ops {
+  void (*ets_delay_us)(uint32_t us);
+} ets_ops;
 
 /**
   * @}

components/esp_rom/esp32c61/ld/esp32c61.rom.ld

@@ -23,7 +23,7 @@ ets_install_putc2 = 0x4000002c;
 ets_install_uart_printf = 0x40000030;
 ets_install_usb_printf = 0x40000034;
 ets_get_printf_channel = 0x40000038;
-ets_delay_us = 0x4000003c;
+PROVIDE ( ets_delay_us = 0x4000003c );
 ets_get_cpu_frequency = 0x40000040;
 ets_update_cpu_frequency = 0x40000044;
 ets_install_lock = 0x40000048;