feat(esp32h4): ci enable public header check (stage7)

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -139,6 +139,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
     bool
     default y
 
+config SOC_GPIO_IN_RANGE_MAX
+    int
+    default 39
+
+config SOC_GPIO_OUT_RANGE_MAX
+    int
+    default 39
+
 config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
     int
     default 0

components/soc/esp32h4/include/soc/gdma_channel.h

@@ -0,0 +1,5 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

components/soc/esp32h4/include/soc/soc_caps.h

@@ -203,6 +203,10 @@
 
 #define SOC_GPIO_VALID_GPIO_MASK        ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
+
+#define SOC_GPIO_IN_RANGE_MAX           39
+#define SOC_GPIO_OUT_RANGE_MAX          39
+
 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
 
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)

components/soc/esp32h4/include/soc/system_intr.h

@@ -0,0 +1,13 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+// Maps misc system interrupt to hardware interrupt names
+#define SYS_CPU_INTR_FROM_CPU_0_SOURCE  ETS_CPU_INTR_FROM_CPU_0_SOURCE
+#define SYS_CPU_INTR_FROM_CPU_1_SOURCE  ETS_CPU_INTR_FROM_CPU_1_SOURCE
+
+#define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_INTR_SOURCE
+#define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_INTR_SOURCE

components/soc/esp32h4/include/soc/system_reg.h

@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/hp_system_reg.h"
+#include "soc/intpri_reg.h"
+
+#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
+#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_1_REG INTPRI_CPU_INTR_FROM_CPU_1_REG
+#define SYSTEM_CPU_INTR_FROM_CPU_1 INTPRI_CPU_INTR_FROM_CPU_1