mirror of
https://github.com/espressif/esp-idf.git
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remove(legacy_dac): remove legacy dac driver in IDF v6.0
This commit is contained in:
laokaiyao
@@ -1,144 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "esp_check.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_private/gpio.h"
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#include "driver/dac_types_legacy.h"
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#include "soc/dac_periph.h"
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#include "hal/gpio_types.h"
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#include "hal/dac_ll.h"
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#include "clk_ctrl_os.h"
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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static __attribute__((unused)) const char *TAG = "DAC";
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/*---------------------------------------------------------------
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DAC
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---------------------------------------------------------------*/
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esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num)
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{
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ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
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*gpio_num = (gpio_num_t)dac_periph_signal.dac_channel_io_num[channel];
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return ESP_OK;
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}
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static esp_err_t dac_rtc_pad_init(dac_channel_t channel)
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{
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ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
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gpio_num_t gpio_num = 0;
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dac_pad_get_io_num(channel, &gpio_num);
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gpio_config_as_analog(gpio_num);
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return ESP_OK;
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}
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esp_err_t dac_output_enable(dac_channel_t channel)
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{
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ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
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dac_rtc_pad_init(channel);
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portENTER_CRITICAL(&rtc_spinlock);
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dac_ll_power_on(channel);
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dac_ll_rtc_sync_by_adc(false);
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portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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esp_err_t dac_output_disable(dac_channel_t channel)
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{
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ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
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portENTER_CRITICAL(&rtc_spinlock);
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dac_ll_power_down(channel);
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portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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esp_err_t dac_output_voltage(dac_channel_t channel, uint8_t dac_value)
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{
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ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
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portENTER_CRITICAL(&rtc_spinlock);
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dac_ll_update_output_value(channel, dac_value);
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portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value)
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{
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ESP_RETURN_ON_FALSE(channel < SOC_DAC_CHAN_NUM, ESP_ERR_INVALID_ARG, TAG, "DAC channel error");
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portENTER_CRITICAL(&rtc_spinlock);
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dac_ll_update_output_value(channel, dac_value);
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portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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esp_err_t dac_cw_generator_enable(void)
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{
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portENTER_CRITICAL(&rtc_spinlock);
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periph_rtc_dig_clk8m_enable();
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dac_ll_cw_generator_enable();
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portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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esp_err_t dac_cw_generator_disable(void)
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{
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portENTER_CRITICAL(&rtc_spinlock);
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dac_ll_cw_generator_disable();
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periph_rtc_dig_clk8m_disable();
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portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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esp_err_t dac_cw_generator_config(dac_cw_config_t *cw)
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{
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ESP_RETURN_ON_FALSE(cw, ESP_ERR_INVALID_ARG, TAG, "invalid clock configuration");
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portENTER_CRITICAL(&rtc_spinlock);
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/* Enable the rtc8m clock temporary to get the correct frequency */
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periph_rtc_dig_clk8m_enable();
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uint32_t rtc_freq = periph_rtc_dig_clk8m_get_freq();
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periph_rtc_dig_clk8m_disable();
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dac_ll_cw_set_freq(cw->freq, rtc_freq);
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dac_ll_cw_set_atten(cw->en_ch, (dac_cosine_atten_t)cw->scale);
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dac_ll_cw_set_phase(cw->en_ch, (dac_cosine_phase_t)cw->phase);
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dac_ll_cw_set_dc_offset(cw->en_ch, cw->offset);
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dac_ll_cw_enable_channel(cw->en_ch, true);
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portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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#if !CONFIG_DAC_SKIP_LEGACY_CONFLICT_CHECK
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/**
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* @brief This function will be called during start up, to check that this legacy DAC driver is not running along with the new driver
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*/
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__attribute__((constructor))
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static void check_dac_legacy_driver_conflict(void)
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{
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// This function was declared as weak here. The new DAC driver has one implementation.
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// So if the new DAC driver is not linked in, then `dac_priv_register_channel()` should be NULL at runtime.
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extern __attribute__((weak)) esp_err_t dac_priv_register_channel(dac_channel_t chan_id, const char *mode_name);
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if ((void *)dac_priv_register_channel != NULL) {
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ESP_EARLY_LOGE(TAG, "CONFLICT! The new DAC driver is not allowed to be used together with the legacy driver");
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abort();
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}
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ESP_EARLY_LOGW(TAG, "legacy driver is deprecated, please migrate to `driver/dac_oneshot.h`, `driver/dac_cosine.h` or `driver/dac_continuous.h` instead");
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}
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#endif //CONFIG_DAC_SKIP_LEGACY_CONFLICT_CHECK
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@@ -1,171 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "esp_err.h"
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#include "sdkconfig.h"
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#include "driver/gpio.h"
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#include "driver/dac_types_legacy.h"
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#if !CONFIG_DAC_SUPPRESS_DEPRECATE_WARN
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#warning "The legacy DAC driver is deprecated, please use `driver/dac_oneshot.h`, `driver/dac_cosine.h` or `driver/dac_continuous.h` instead"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Get the GPIO number of a specific DAC channel.
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*
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* @param channel Channel to get the gpio number
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* @param gpio_num output buffer to hold the gpio number
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* @return
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* - ESP_OK if success
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*/
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esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num);
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/**
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* @brief Set DAC output voltage.
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* DAC output is 8-bit. Maximum (255) corresponds to VDD3P3_RTC.
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*
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* @note Need to configure DAC pad before calling this function.
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* DAC channel 0 is attached to GPIO25, DAC channel 1 is attached to GPIO26
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* @param channel DAC channel
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* @param dac_value DAC output value
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*
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_output_voltage(dac_channel_t channel, uint8_t dac_value);
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/**
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* @brief DAC pad output enable
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*
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* @param channel DAC channel
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* @note DAC channel 0 is attached to GPIO25, DAC channel 1 is attached to GPIO26
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* I2S left channel will be mapped to DAC channel 1
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* I2S right channel will be mapped to DAC channel 0
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*/
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esp_err_t dac_output_enable(dac_channel_t channel);
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/**
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* @brief DAC pad output disable
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*
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* @param channel DAC channel
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* @note DAC channel 0 is attached to GPIO25, DAC channel 1 is attached to GPIO26
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_output_disable(dac_channel_t channel);
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/**
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* @brief Enable cosine wave generator output.
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*
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_cw_generator_enable(void);
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/**
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* @brief Disable cosine wave generator output.
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*
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_cw_generator_disable(void);
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/**
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* @brief Config the cosine wave generator function in DAC module.
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*
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* @param cw Configuration.
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* @return
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* - ESP_OK success
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* - ESP_ERR_INVALID_ARG The parameter is NULL.
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*/
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esp_err_t dac_cw_generator_config(dac_cw_config_t *cw);
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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#if CONFIG_IDF_TARGET_ESP32
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/**
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* @brief Enable DAC output data from I2S
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*
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_i2s_enable(void);
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/**
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* @brief Disable DAC output data from I2S
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*
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_i2s_disable(void);
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#endif // CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief DAC digital controller initialization.
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_digi_init(void);
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/**
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* @brief DAC digital controller deinitialization.
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_digi_deinit(void);
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/**
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* @brief Setting the DAC digital controller.
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*
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* @param cfg Pointer to digital controller parameter. See ``dac_digi_config_t``.
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*
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* @return
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* - ESP_OK success
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* - ESP_ERR_INVALID_ARG Parameter error
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*/
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esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg);
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/**
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* @brief DAC digital controller start output voltage.
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_digi_start(void);
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/**
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* @brief DAC digital controller stop output voltage.
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_digi_stop(void);
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/**
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* @brief Reset DAC digital controller FIFO.
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_digi_fifo_reset(void);
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/**
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* @brief Reset DAC digital controller.
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* @return
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* - ESP_OK success
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*/
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esp_err_t dac_digi_reset(void);
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#endif // CONFIG_IDF_TARGET_ESP32S2
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#ifdef __cplusplus
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}
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#endif
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@@ -1,79 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include "sdkconfig.h"
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#include "hal/dac_types.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "hal/adc_types.h"
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief The multiple of the amplitude of the cosine wave generator. The max amplitude is VDD3P3_RTC.
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*/
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typedef enum {
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DAC_CW_SCALE_1 = 0x0, /*!< 1/1. Default. */
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DAC_CW_SCALE_2 = 0x1, /*!< 1/2. */
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DAC_CW_SCALE_4 = 0x2, /*!< 1/4. */
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DAC_CW_SCALE_8 = 0x3, /*!< 1/8. */
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} dac_cw_scale_t;
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/**
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* @brief Set the phase of the cosine wave generator output.
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*/
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typedef enum {
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DAC_CW_PHASE_0 = 0x2, /*!< Phase shift +0° */
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DAC_CW_PHASE_180 = 0x3, /*!< Phase shift +180° */
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} dac_cw_phase_t;
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#if CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief DAC digital controller (DMA mode) work mode.
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*/
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typedef enum {
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DAC_CONV_NORMAL, /*!< The data in the DMA buffer is simultaneously output to the enable channel of the DAC. */
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DAC_CONV_ALTER, /*!< The data in the DMA buffer is alternately output to the enable channel of the DAC. */
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DAC_CONV_MAX
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} dac_digi_convert_mode_t;
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/**
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* @brief DAC digital controller (DMA mode) configuration parameters.
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*/
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typedef struct {
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dac_digi_convert_mode_t mode; /*!<DAC digital controller (DMA mode) work mode. See ``dac_digi_convert_mode_t``. */
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uint32_t interval; /*!<The number of interval clock cycles for the DAC digital controller to output voltage.
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The unit is the divided clock. Range: 1 ~ 4095.
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Expression: `dac_output_freq` = `controller_clk` / interval. Refer to ``adc_digi_clk_t``.
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Note: The sampling rate of each channel is also related to the conversion mode (See ``dac_digi_convert_mode_t``) and pattern table settings. */
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adc_digi_clk_t dig_clk; /*!<DAC digital controller clock divider settings. Refer to ``adc_digi_clk_t``.
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Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */
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} dac_digi_config_t;
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#endif
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/**
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* @brief Config the cosine wave generator function in DAC module.
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*/
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typedef struct {
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dac_channel_t en_ch; /*!< Enable the cosine wave generator of DAC channel. */
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dac_cw_scale_t scale; /*!< Set the amplitude of the cosine wave generator output. */
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dac_cw_phase_t phase; /*!< Set the phase of the cosine wave generator output. */
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uint32_t freq; /*!< Set frequency of cosine wave generator output. Range: 130(130Hz) ~ 55000(100KHz). */
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int8_t offset; /*!< Set the voltage value of the DC component of the cosine wave generator output.
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Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */
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} dac_cw_config_t;
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#ifdef __cplusplus
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}
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#endif
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@@ -1,35 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
|
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*/
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#include "freertos/FreeRTOS.h"
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#include "hal/dac_ll.h"
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#include "esp_err.h"
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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#define DAC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define DAC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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esp_err_t dac_i2s_enable(void)
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{
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DAC_ENTER_CRITICAL();
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dac_ll_digi_enable_dma(true);
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t dac_i2s_disable(void)
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{
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DAC_ENTER_CRITICAL();
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dac_ll_digi_enable_dma(false);
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DAC_EXIT_CRITICAL();
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return ESP_OK;
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}
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@@ -1,135 +0,0 @@
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/*
|
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
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*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
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*/
|
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#include <string.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
|
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#include "driver/dac_types_legacy.h"
|
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#include "hal/adc_ll.h"
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#include "hal/dac_ll.h"
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#include "esp_check.h"
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#include "esp_pm.h"
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|
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static __attribute__((unused)) const char *TAG = "DAC";
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||||
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
|
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#define DAC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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||||
#define DAC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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||||
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||||
#ifdef CONFIG_PM_ENABLE
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static esp_pm_lock_handle_t s_dac_digi_lock = NULL;
|
||||
#endif //CONFIG_PM_ENABLE
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Digital controller setting
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
esp_err_t dac_digi_init(void)
|
||||
{
|
||||
DAC_ENTER_CRITICAL();
|
||||
dac_ll_digi_clk_inv(true);
|
||||
DAC_EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t dac_digi_deinit(void)
|
||||
{
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
if (s_dac_digi_lock) {
|
||||
esp_pm_lock_delete(s_dac_digi_lock);
|
||||
s_dac_digi_lock = NULL;
|
||||
}
|
||||
#endif
|
||||
DAC_ENTER_CRITICAL();
|
||||
dac_ll_digi_trigger_output(false);
|
||||
dac_ll_digi_enable_dma(false);
|
||||
dac_ll_digi_fifo_reset();
|
||||
dac_ll_digi_reset();
|
||||
DAC_EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg)
|
||||
{
|
||||
ESP_RETURN_ON_FALSE(cfg->mode <= DAC_CONV_ALTER, ESP_ERR_INVALID_ARG, TAG, "DAC mode error");
|
||||
ESP_RETURN_ON_FALSE(cfg->interval > 0 && cfg->interval < 4096, ESP_ERR_INVALID_ARG, TAG, "DAC interval error");
|
||||
ESP_RETURN_ON_FALSE(cfg->dig_clk.div_num < 256, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_num error");
|
||||
ESP_RETURN_ON_FALSE(cfg->dig_clk.div_b > 0 && cfg->dig_clk.div_b < 64, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_b error");
|
||||
ESP_RETURN_ON_FALSE(cfg->dig_clk.div_a < 64, ESP_ERR_INVALID_ARG, TAG, "DAC clk div_a error");
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
esp_err_t err;
|
||||
if (s_dac_digi_lock == NULL) {
|
||||
if (cfg->dig_clk.use_apll) {
|
||||
err = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "dac_dma", &s_dac_digi_lock);
|
||||
} else {
|
||||
err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "dac_dma", &s_dac_digi_lock);
|
||||
}
|
||||
if (err != ESP_OK) {
|
||||
s_dac_digi_lock = NULL;
|
||||
ESP_LOGE(TAG, "DAC-DMA pm lock error");
|
||||
return err;
|
||||
}
|
||||
}
|
||||
#endif //CONFIG_PM_ENABLE
|
||||
|
||||
DAC_ENTER_CRITICAL();
|
||||
dac_ll_digi_set_convert_mode(cfg->mode == DAC_CONV_ALTER);
|
||||
dac_ll_digi_set_trigger_interval(cfg->interval);
|
||||
adc_ll_digi_controller_clk_div(cfg->dig_clk.div_num, cfg->dig_clk.div_b, cfg->dig_clk.div_a);
|
||||
adc_ll_digi_clk_sel(cfg->dig_clk.use_apll ? ADC_DIGI_CLK_SRC_APLL : ADC_DIGI_CLK_SRC_DEFAULT);
|
||||
DAC_EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t dac_digi_start(void)
|
||||
{
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
ESP_RETURN_ON_FALSE(s_dac_digi_lock, ESP_FAIL, TAG, "Should start after call `dac_digi_controller_config`");
|
||||
esp_pm_lock_acquire(s_dac_digi_lock);
|
||||
#endif
|
||||
DAC_ENTER_CRITICAL();
|
||||
dac_ll_digi_enable_dma(true);
|
||||
dac_ll_digi_trigger_output(true);
|
||||
DAC_EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t dac_digi_stop(void)
|
||||
{
|
||||
#ifdef CONFIG_PM_ENABLE
|
||||
if (s_dac_digi_lock) {
|
||||
esp_pm_lock_release(s_dac_digi_lock);
|
||||
}
|
||||
#endif
|
||||
DAC_ENTER_CRITICAL();
|
||||
dac_ll_digi_trigger_output(false);
|
||||
dac_ll_digi_enable_dma(false);
|
||||
DAC_EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t dac_digi_fifo_reset(void)
|
||||
{
|
||||
DAC_ENTER_CRITICAL();
|
||||
dac_ll_digi_fifo_reset();
|
||||
DAC_EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t dac_digi_reset(void)
|
||||
{
|
||||
DAC_ENTER_CRITICAL();
|
||||
dac_ll_digi_reset();
|
||||
DAC_EXIT_CRITICAL();
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
Reference in New Issue
Block a user