fix(mspi): fixed possible boot failure in some builds when psram is enabled

A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.

The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.

This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.

components/esp_tee/scripts/esp32c5/sec_srv_tbl_default.yml

@@ -120,6 +120,14 @@ secure_services:
         type: IDF
         function: spi_timing_get_flash_timing_param
         args: 1
+      - id: 29
+        type: IDF
+        function: mspi_timing_enter_low_speed_early
+        args: 0
+      - id: 10
+        type: IDF
+        function: mspi_timing_enter_high_speed_early
+        args: 0
   # ID: 30-53 (24) - Interrupt Handling
   - family: interrupt_handling
     entries: