soc: Add a soc cap, SOC_CLK_RC_FAST_D256_SUPPORTED, for whether the target has the RC_FAST_D256 clock

components/esp_hw_support/clk_ctrl_os.c

@@ -26,7 +26,7 @@ bool periph_rtc_dig_clk8m_enable(void)
     portENTER_CRITICAL(&periph_spinlock);
     if (s_periph_ref_counts == 0) {
         rtc_dig_clk8m_enable();
-#if !CONFIG_IDF_TARGET_ESP32H2
+#if SOC_CLK_RC_FAST_D256_SUPPORTED
         s_rtc_clk_freq = rtc_clk_freq_cal(rtc_clk_cal(RTC_CAL_8MD256, 100));
         if (s_rtc_clk_freq == 0) {
             portEXIT_CRITICAL(&periph_spinlock);
@@ -41,8 +41,8 @@ bool periph_rtc_dig_clk8m_enable(void)
 
 uint32_t periph_rtc_dig_clk8m_get_freq(void)
 {
-#if CONFIG_IDF_TARGET_ESP32H2
-    /* Workaround: H2 doesn't have 8MD256 clk, so calibration cannot be done, we just return its theoretic frequency */
+#if !SOC_CLK_RC_FAST_D256_SUPPORTED
+    /* Workaround: CLK8M calibration cannot be performed if there is no d256 div clk, we can only return its theoretic value */
     return SOC_CLK_RC_FAST_FREQ_APPROX;
 #else
     return s_rtc_clk_freq * 256;

components/esp_hw_support/sleep_modes.c

@@ -401,8 +401,8 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
         suspend_uarts();
     }
 
-#if SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
-    //Keep the RTC8M_CLK on if RTC clock is 8MD256.
+#if SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
+    //Keep the RTC8M_CLK on if RTC clock is rc_fast_d256.
     bool rtc_using_8md256 = (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256);
 #else
     bool rtc_using_8md256 = false;

components/esp_hw_support/test_apps/dma/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |