mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'change/delete_not_used_mmu_macros' into 'master'
mm: delete not used mmu macros and added soc_ prefix Closes IDF-7686 See merge request espressif/esp-idf!25663
This commit is contained in:
Armando (Dou Yiwen)
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -13,45 +13,45 @@
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extern "C" {
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#endif
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#define IRAM0_CACHE_ADDRESS_LOW 0x400D0000
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#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
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#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x400D0000
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#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x40400000
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#define IRAM1_CACHE_ADDRESS_LOW 0x40400000
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#define IRAM1_CACHE_ADDRESS_HIGH 0x40800000
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#define SOC_IRAM1_CACHE_ADDRESS_LOW 0x40400000
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#define SOC_IRAM1_CACHE_ADDRESS_HIGH 0x40800000
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#define IROM0_CACHE_ADDRESS_LOW 0x40800000
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#define IROM0_CACHE_ADDRESS_HIGH 0x40C00000
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#define SOC_IROM0_CACHE_ADDRESS_LOW 0x40800000
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#define SOC_IROM0_CACHE_ADDRESS_HIGH 0x40C00000
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#define DRAM1_CACHE_ADDRESS_LOW 0x3F800000
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#define DRAM1_CACHE_ADDRESS_HIGH 0x3FC00000
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#define SOC_DRAM1_CACHE_ADDRESS_LOW 0x3F800000
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#define SOC_DRAM1_CACHE_ADDRESS_HIGH 0x3FC00000
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#define DROM0_CACHE_ADDRESS_LOW 0x3F400000
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#define DROM0_CACHE_ADDRESS_HIGH 0x3F800000
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#define SOC_DROM0_CACHE_ADDRESS_LOW 0x3F400000
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#define SOC_DROM0_CACHE_ADDRESS_HIGH 0x3F800000
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#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
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#define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr)
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#define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr)
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#define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr)
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#define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr)
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#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
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#define SOC_ADDRESS_IN_IRAM1_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM1_CACHE, vaddr)
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#define SOC_ADDRESS_IN_IROM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IROM0_CACHE, vaddr)
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#define SOC_ADDRESS_IN_DRAM1_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM1_CACHE, vaddr)
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#define SOC_ADDRESS_IN_DROM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DROM0_CACHE, vaddr)
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#define MMU_INVALID BIT(8)
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#define SOC_MMU_INVALID BIT(8)
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/**
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* Max MMU available paddr page num.
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* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
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* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
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* 256 * 64KB, means MMU can support 16MB paddr at most
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*/
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#define MMU_MAX_PADDR_PAGE_NUM 256
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#define SOC_MMU_MAX_PADDR_PAGE_NUM 256
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/**
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* This is the mask used for mapping. e.g.:
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* 0x4008_0000 & MMU_VADDR_MASK
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* 0x4008_0000 & SOC_MMU_VADDR_MASK
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*/
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#define MMU_VADDR_MASK 0x3FFFFF
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#define SOC_MMU_VADDR_MASK 0x3FFFFF
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//MMU entry num, 384 entries that are used in IDF for Flash
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#define MMU_ENTRY_NUM 384
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#define SOC_MMU_ENTRY_NUM 384
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#define SOC_MMU_DBUS_VADDR_BASE 0x3E000000
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@@ -68,20 +68,20 @@ extern "C" {
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*/
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#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (IRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (IRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (SOC_IRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (SOC_IRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IROM0_LINEAR_ADDRESS_LOW (IROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IROM0_LINEAR_ADDRESS_HIGH (IROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IROM0_LINEAR_ADDRESS_LOW (SOC_IROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IROM0_LINEAR_ADDRESS_HIGH (SOC_IROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (DROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (DROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (SOC_DROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (SOC_DROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (DRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (DRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (SOC_DRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (SOC_DRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -23,91 +23,50 @@ extern "C" {
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/*IRAM0 is connected with Cache IBUS0*/
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#define IRAM0_ADDRESS_LOW 0x4037C000
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#define IRAM0_ADDRESS_HIGH 0x403C0000
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#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
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#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
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#define SOC_IRAM0_ADDRESS_LOW 0x4037C000
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#define SOC_IRAM0_ADDRESS_HIGH 0x403C0000
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#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
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#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) // MMU has 64 pages
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/*DRAM0 is connected with Cache DBUS0*/
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#define DRAM0_ADDRESS_LOW 0x3FCA0000
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#define DRAM0_ADDRESS_HIGH 0x3FCE0000
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#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
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#define DRAM0_CACHE_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
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#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
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#define SOC_DRAM0_ADDRESS_LOW 0x3FCA0000
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#define SOC_DRAM0_ADDRESS_HIGH 0x3FCE0000
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#define SOC_DRAM0_CACHE_ADDRESS_LOW 0x3C000000
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#define SOC_DRAM0_CACHE_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) // MMU has 64 pages
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#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
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#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
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#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
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#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
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#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
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#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
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#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
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#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
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#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
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#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
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#define CACHE_IBUS 0
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#define CACHE_IBUS_MMU_START 0
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#define CACHE_IBUS_MMU_END 0x100
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#define CACHE_DBUS 1
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#define CACHE_DBUS_MMU_START 0
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#define CACHE_DBUS_MMU_END 0x100
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//TODO, remove these cache function dependencies
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#define CACHE_IROM_MMU_START 0
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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#define CACHE_DROM_MMU_MAX_END 0x100
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#define ICACHE_MMU_SIZE 0x100
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#define DCACHE_MMU_SIZE 0x100
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#define MMU_BUS_START(i) 0
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#define MMU_BUS_SIZE(i) 0x100
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#define MMU_INVALID BIT(6)
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#define MMU_VALID 0
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#define MMU_TYPE 0
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#define MMU_ACCESS_FLASH 0
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#define CACHE_MAX_SYNC_NUM 0x400000
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#define CACHE_MAX_LOCK_NUM 0x8000
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#define SOC_MMU_INVALID BIT(6)
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#define SOC_MMU_VALID 0
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#define SOC_MMU_TYPE 0
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#define SOC_MMU_ACCESS_FLASH 0
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/**
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* MMU entry valid bit mask for mapping value. For an entry:
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* valid bit + value bits
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* valid bit is BIT(6), so value bits are 0x3f
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*/
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#define MMU_VALID_VAL_MASK 0x3f
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#define SOC_MMU_VALID_VAL_MASK 0x3f
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/**
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* Max MMU available paddr page num.
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* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
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* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
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* 64 * 64KB, means MMU can support 4MB paddr at most
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*/
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#define MMU_MAX_PADDR_PAGE_NUM 64
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#define SOC_MMU_MAX_PADDR_PAGE_NUM 64
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/**
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* This is the mask used for mapping. e.g.:
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* 0x4200_0000 & MMU_VADDR_MASK
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* 0x4200_0000 & SOC_MMU_VADDR_MASK
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*/
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#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * 64 - 1)
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#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * 64 - 1)
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//MMU entry num
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#define MMU_ENTRY_NUM 64
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#define BUS_PMS_MASK 0xffffff
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#define CACHE_ICACHE_LOW_SHIFT 0
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#define CACHE_ICACHE_HIGH_SHIFT 2
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#define CACHE_DCACHE_LOW_SHIFT 4
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#define CACHE_DCACHE_HIGH_SHIFT 6
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#define CACHE_MEMORY_IBANK0_ADDR 0x4037C000
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#define SOC_MMU_ENTRY_NUM 64
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#define SOC_MMU_DBUS_VADDR_BASE 0x3C000000
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#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
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@@ -148,16 +107,16 @@ extern "C" {
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* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
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* Under this condition, we use the max linear space.
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*/
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#else
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
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#endif
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#else
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
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#endif
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@@ -168,6 +127,36 @@ extern "C" {
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_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
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/**
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* ROM flash mmap driver needs below definitions
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*/
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#define BUS_IRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_IRAM0_CACHE)
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#define BUS_DRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_DRAM0_CACHE)
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#define CACHE_IBUS 0
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#define CACHE_IBUS_MMU_START 0
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#define CACHE_IBUS_MMU_END 0x100
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#define CACHE_DBUS 1
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#define CACHE_DBUS_MMU_START 0
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#define CACHE_DBUS_MMU_END 0x100
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#define CACHE_IROM_MMU_START 0
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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#define CACHE_DROM_MMU_MAX_END 0x100
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#define ICACHE_MMU_SIZE 0x100
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#define DCACHE_MMU_SIZE 0x100
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#define MMU_BUS_START(i) 0
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#define MMU_BUS_SIZE(i) 0x100
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#ifdef __cplusplus
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}
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#endif
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@@ -20,9 +20,9 @@ extern "C" {
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#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
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#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
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#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
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#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
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#define SOC_MMU_ADDR_MASK SOC_MMU_VALID_VAL_MASK
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#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
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#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
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||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM0_CACHE_ADDRESS_LOW
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#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
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#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
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||||
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
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||||
@@ -1,10 +1,9 @@
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/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _CACHE_MEMORY_H_
|
||||
#define _CACHE_MEMORY_H_
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
@@ -13,88 +12,49 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/*IRAM0 is connected with Cache IBUS0*/
|
||||
#define IRAM0_ADDRESS_LOW 0x4037C000
|
||||
#define IRAM0_ADDRESS_HIGH 0x403E0000
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH 0x42800000
|
||||
#define SOC_IRAM0_ADDRESS_LOW 0x4037C000
|
||||
#define SOC_IRAM0_ADDRESS_HIGH 0x403E0000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x42800000
|
||||
|
||||
/*DRAM0 is connected with Cache DBUS0*/
|
||||
#define DRAM0_ADDRESS_LOW 0x3FC80000
|
||||
#define DRAM0_ADDRESS_HIGH 0x3FCE0000
|
||||
#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH 0x3C800000
|
||||
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
|
||||
#define SOC_DRAM0_ADDRESS_LOW 0x3FC80000
|
||||
#define SOC_DRAM0_ADDRESS_HIGH 0x3FCE0000
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW 0x3C000000
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH 0x3C800000
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
|
||||
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
|
||||
|
||||
#define CACHE_IBUS 0
|
||||
#define CACHE_IBUS_MMU_START 0
|
||||
#define CACHE_IBUS_MMU_END 0x200
|
||||
|
||||
#define CACHE_DBUS 1
|
||||
#define CACHE_DBUS_MMU_START 0
|
||||
#define CACHE_DBUS_MMU_END 0x200
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x200
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#define MMU_INVALID BIT(8)
|
||||
#define MMU_VALID 0
|
||||
#define MMU_TYPE 0
|
||||
#define MMU_ACCESS_FLASH 0
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM 0x400000
|
||||
#define CACHE_MAX_LOCK_NUM 0x8000
|
||||
#define SOC_MMU_INVALID BIT(8)
|
||||
#define SOC_MMU_VALID 0
|
||||
#define SOC_MMU_TYPE 0
|
||||
#define SOC_MMU_ACCESS_FLASH 0
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(8), so value bits are 0xff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0xff
|
||||
#define SOC_MMU_VALID_VAL_MASK 0xff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 256 * 64KB, means MMU can support 16MB paddr at most
|
||||
*/
|
||||
#define MMU_MAX_PADDR_PAGE_NUM 256
|
||||
#define SOC_MMU_MAX_PADDR_PAGE_NUM 256
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
* 0x4200_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK 0x7FFFFF
|
||||
#define SOC_MMU_VADDR_MASK 0x7FFFFF
|
||||
//MMU entry num
|
||||
#define MMU_ENTRY_NUM 128
|
||||
|
||||
#define CACHE_ICACHE_LOW_SHIFT 0
|
||||
#define CACHE_ICACHE_HIGH_SHIFT 2
|
||||
#define CACHE_DCACHE_LOW_SHIFT 4
|
||||
#define CACHE_DCACHE_HIGH_SHIFT 6
|
||||
|
||||
#define CACHE_MEMORY_IBANK0_ADDR 0x4037c000
|
||||
#define SOC_MMU_ENTRY_NUM 128
|
||||
|
||||
#define SOC_MMU_DBUS_VADDR_BASE 0x3C000000
|
||||
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
|
||||
@@ -115,16 +75,16 @@ extern "C" {
|
||||
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
|
||||
* Under this condition, we use the max linear space.
|
||||
*/
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
@@ -135,8 +95,36 @@ extern "C" {
|
||||
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
|
||||
|
||||
|
||||
/**
|
||||
* ROM flash mmap driver needs below definitions
|
||||
*/
|
||||
#define BUS_IRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_DRAM0_CACHE)
|
||||
|
||||
#define CACHE_IBUS 0
|
||||
#define CACHE_IBUS_MMU_START 0
|
||||
#define CACHE_IBUS_MMU_END 0x200
|
||||
|
||||
#define CACHE_DBUS 1
|
||||
#define CACHE_DBUS_MMU_START 0
|
||||
#define CACHE_DBUS_MMU_END 0x200
|
||||
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x200
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_CACHE_MEMORY_H_ */
|
||||
|
||||
@@ -20,9 +20,9 @@ extern "C" {
|
||||
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_ADDR_MASK SOC_MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
|
||||
|
||||
@@ -20,81 +20,46 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
|
||||
|
||||
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
|
||||
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#define MMU_MSPI_ACCESS_FLASH 0
|
||||
#define MMU_MSPI_VALID BIT(9)
|
||||
#define MMU_MSPI_INVALID 0
|
||||
#define MMU_MSPI_SENSITIVE BIT(10)
|
||||
|
||||
#define MMU_ACCESS_FLASH MMU_MSPI_ACCESS_FLASH
|
||||
#define MMU_VALID MMU_MSPI_VALID
|
||||
#define MMU_SENSITIVE MMU_MSPI_SENSITIVE
|
||||
|
||||
#define MMU_INVALID_MASK MMU_MSPI_VALID
|
||||
#define MMU_INVALID MMU_MSPI_INVALID
|
||||
|
||||
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM 0x400000
|
||||
#define CACHE_MAX_LOCK_NUM 0x8000
|
||||
#define SOC_MMU_ACCESS_FLASH 0
|
||||
#define SOC_MMU_VALID BIT(9)
|
||||
#define SOC_MMU_SENSITIVE BIT(10)
|
||||
#define SOC_MMU_INVALID_MASK BIT(9)
|
||||
#define SOC_MMU_INVALID 0
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(9), so value bits are 0x1ff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0x1ff
|
||||
#define SOC_MMU_VALID_VAL_MASK 0x1ff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 256 * 64KB, means MMU can support 16MB paddr at most
|
||||
*/
|
||||
#define MMU_MAX_PADDR_PAGE_NUM 256
|
||||
#define SOC_MMU_MAX_PADDR_PAGE_NUM 256
|
||||
//MMU entry num
|
||||
#define MMU_ENTRY_NUM 256
|
||||
#define SOC_MMU_ENTRY_NUM 256
|
||||
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
* 0x4200_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
|
||||
|
||||
#define CACHE_MEMORY_IBANK0_ADDR 0x40800000
|
||||
|
||||
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
#define SOC_MMU_DBUS_VADDR_BASE 0x42000000
|
||||
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
|
||||
@@ -135,16 +100,16 @@ extern "C" {
|
||||
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
|
||||
* Under this condition, we use the max linear space.
|
||||
*/
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
@@ -155,6 +120,25 @@ extern "C" {
|
||||
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
|
||||
|
||||
|
||||
/**
|
||||
* ROM flash mmap driver needs below definitions
|
||||
*/
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -21,9 +21,9 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
||||
#define SOC_MMU_ADDR_MASK (MMU_VALID - 1)
|
||||
#define SOC_MMU_ADDR_MASK (SOC_MMU_VALID - 1)
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -20,81 +20,46 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
|
||||
|
||||
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
|
||||
#define BUS_IRAM0_CACHE_SIZE(page_size) BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE(page_size) BUS_SIZE(DRAM0_CACHE)
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#define MMU_MSPI_ACCESS_FLASH 0
|
||||
#define MMU_MSPI_VALID BIT(9)
|
||||
#define MMU_MSPI_INVALID 0
|
||||
#define MMU_MSPI_SENSITIVE BIT(10)
|
||||
|
||||
#define MMU_ACCESS_FLASH MMU_MSPI_ACCESS_FLASH
|
||||
#define MMU_VALID MMU_MSPI_VALID
|
||||
#define MMU_SENSITIVE MMU_MSPI_SENSITIVE
|
||||
|
||||
#define MMU_INVALID_MASK MMU_MSPI_VALID
|
||||
#define MMU_INVALID MMU_MSPI_INVALID
|
||||
|
||||
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM 0x400000
|
||||
#define CACHE_MAX_LOCK_NUM 0x8000
|
||||
#define SOC_MMU_ACCESS_FLASH 0
|
||||
#define SOC_MMU_VALID BIT(9)
|
||||
#define SOC_MMU_SENSITIVE BIT(10)
|
||||
#define SOC_MMU_INVALID_MASK BIT(9)
|
||||
#define SOC_MMU_INVALID 0
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(9), so value bits are 0x1ff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0x1ff
|
||||
#define SOC_MMU_VALID_VAL_MASK 0x1ff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 256 * 64KB, means MMU can support 16MB paddr at most
|
||||
*/
|
||||
#define MMU_MAX_PADDR_PAGE_NUM 256
|
||||
#define SOC_MMU_MAX_PADDR_PAGE_NUM 256
|
||||
//MMU entry num
|
||||
#define MMU_ENTRY_NUM 256
|
||||
#define SOC_MMU_ENTRY_NUM 256
|
||||
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
* 0x4200_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
|
||||
|
||||
#define CACHE_MEMORY_IBANK0_ADDR 0x40800000
|
||||
|
||||
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
#define SOC_MMU_DBUS_VADDR_BASE 0x42000000
|
||||
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
|
||||
@@ -135,16 +100,16 @@ extern "C" {
|
||||
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
|
||||
* Under this condition, we use the max linear space.
|
||||
*/
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
@@ -155,6 +120,28 @@ extern "C" {
|
||||
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
|
||||
|
||||
|
||||
/**
|
||||
* ROM flash mmap driver needs below definitions
|
||||
*/
|
||||
#define BUS_IRAM0_CACHE_SIZE(page_size) SOC_BUS_SIZE(SOC_IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE(page_size) SOC_BUS_SIZE(SOC_DRAM0_CACHE)
|
||||
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -21,9 +21,9 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
|
||||
#define SOC_MMU_ADDR_MASK (MMU_VALID - 1)
|
||||
#define SOC_MMU_ADDR_MASK (SOC_MMU_VALID - 1)
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
|
||||
|
||||
@@ -20,59 +20,39 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x40000000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH 0x50000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x40000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x50000000
|
||||
|
||||
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
|
||||
#define DRAM_FLASH_ADDRESS_LOW DRAM0_CACHE_ADDRESS_LOW
|
||||
#define DRAM_FLASH_ADDRESS_HIGH 0x44000000
|
||||
#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_DRAM_FLASH_ADDRESS_HIGH 0x44000000
|
||||
|
||||
#define DRAM_PSRAM_ADDRESS_LOW 0x48000000
|
||||
#define DRAM_PSRAM_ADDRESS_HIGH 0x4C000000
|
||||
#define SOC_DRAM_PSRAM_ADDRESS_LOW 0x48000000
|
||||
#define SOC_DRAM_PSRAM_ADDRESS_HIGH 0x4C000000
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM_FLASH(vaddr) ADDRESS_IN_BUS(DRAM_FLASH, vaddr)
|
||||
#define ADDRESS_IN_DRAM_PSRAM(vaddr) ADDRESS_IN_BUS(DRAM_PSRAM, vaddr)
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE (0x400 * 4)
|
||||
#define DCACHE_MMU_SIZE (0x400 * 4)
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) (0x400 * 4)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM_FLASH(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM_FLASH, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM_PSRAM(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM_PSRAM, vaddr)
|
||||
|
||||
|
||||
#define MMU_FLASH_VALID BIT(12)
|
||||
#define MMU_FLASH_INVALID 0
|
||||
#define MMU_PSRAM_VALID BIT(11)
|
||||
#define MMU_PSRAM_INVALID 0
|
||||
#define SOC_MMU_FLASH_VALID BIT(12)
|
||||
#define SOC_MMU_FLASH_INVALID 0
|
||||
#define SOC_MMU_PSRAM_VALID BIT(11)
|
||||
#define SOC_MMU_PSRAM_INVALID 0
|
||||
|
||||
#define MMU_ACCESS_FLASH 0
|
||||
#define MMU_ACCESS_PSRAM BIT(10)
|
||||
#define SOC_MMU_ACCESS_FLASH 0
|
||||
#define SOC_MMU_ACCESS_PSRAM BIT(10)
|
||||
|
||||
#define MMU_FLASH_SENSITIVE BIT(13)
|
||||
#define MMU_PSRAM_SENSITIVE BIT(12)
|
||||
#define SOC_MMU_FLASH_SENSITIVE BIT(13)
|
||||
#define SOC_MMU_PSRAM_SENSITIVE BIT(12)
|
||||
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM 0x400000
|
||||
#define CACHE_MAX_LOCK_NUM 0x8000
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value.
|
||||
* - For a Flash MMU entry:
|
||||
@@ -80,26 +60,26 @@ extern "C" {
|
||||
* - For a PSRAM MMU entry:
|
||||
* physical page number is BIT(0)~BIT(9), so value bits are 0x3ff
|
||||
*/
|
||||
#define MMU_FLASH_VALID_VAL_MASK 0x7ff
|
||||
#define MMU_PSRAM_VALID_VAL_MASK 0x3ff
|
||||
#define SOC_MMU_FLASH_VALID_VAL_MASK 0x7ff
|
||||
#define SOC_MMU_PSRAM_VALID_VAL_MASK 0x3ff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 32768 * 64KB, means MMU can support 2GB paddr at most
|
||||
*/
|
||||
#define MMU_FLASH_MAX_PADDR_PAGE_NUM 32768
|
||||
#define MMU_PSRAM_MAX_PADDR_PAGE_NUM 16384
|
||||
#define SOC_MMU_FLASH_MAX_PADDR_PAGE_NUM 32768
|
||||
#define SOC_MMU_PSRAM_MAX_PADDR_PAGE_NUM 16384
|
||||
//MMU entry num
|
||||
#define MMU_ENTRY_NUM 1024
|
||||
#define SOC_MMU_ENTRY_NUM 1024
|
||||
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4000_0000 & MMU_VADDR_MASK
|
||||
* 0x4000_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
|
||||
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
#define SOC_MMU_FLASH_VADDR_BASE 0x40000000
|
||||
#define SOC_MMU_PSRAM_VADDR_BASE 0x48000000
|
||||
#define SOC_MMU_FLASH_VADDR_BASE 0x40000000
|
||||
#define SOC_MMU_PSRAM_VADDR_BASE 0x48000000
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* MMU Linear Address
|
||||
@@ -110,23 +90,23 @@ extern "C" {
|
||||
*
|
||||
* Therefore, 0x3F,FFFF
|
||||
*/
|
||||
#define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFFFF
|
||||
#define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFFFF
|
||||
|
||||
/**
|
||||
* - If high linear address isn't 0, this means MMU can recognize these addresses
|
||||
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
|
||||
* Under this condition, we use the max linear space.
|
||||
*/
|
||||
#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW (DRAM_FLASH_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW (SOC_DRAM_FLASH_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (SOC_DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW (DRAM_PSRAM_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW (SOC_DRAM_PSRAM_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (SOC_DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
@@ -1,21 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//To delete this file
|
||||
//TODO: IDF-7686
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -13,55 +13,55 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/*IRAM0 is connected with Cache IBUS0*/
|
||||
#define IRAM0_ADDRESS_LOW 0x40000000
|
||||
#define IRAM0_ADDRESS_HIGH 0x40400000
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
|
||||
#define SOC_IRAM0_ADDRESS_LOW 0x40000000
|
||||
#define SOC_IRAM0_ADDRESS_HIGH 0x40400000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x40080000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x40400000
|
||||
|
||||
/*IRAM1 is connected with Cache IBUS1*/
|
||||
#define IRAM1_ADDRESS_LOW 0x40400000
|
||||
#define IRAM1_ADDRESS_HIGH 0x40800000
|
||||
#define SOC_IRAM1_ADDRESS_LOW 0x40400000
|
||||
#define SOC_IRAM1_ADDRESS_HIGH 0x40800000
|
||||
|
||||
/*DROM0 is connected with Cache IBUS2*/
|
||||
#define DROM0_ADDRESS_LOW 0x3f000000
|
||||
#define DROM0_ADDRESS_HIGH 0x3f400000
|
||||
#define SOC_DROM0_ADDRESS_LOW 0x3f000000
|
||||
#define SOC_DROM0_ADDRESS_HIGH 0x3f400000
|
||||
|
||||
/*DRAM0 is connected with Cache DBUS0*/
|
||||
#define DRAM0_ADDRESS_LOW 0x3fc00000
|
||||
#define DRAM0_ADDRESS_HIGH 0x40000000
|
||||
#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000
|
||||
#define SOC_DRAM0_ADDRESS_LOW 0x3fc00000
|
||||
#define SOC_DRAM0_ADDRESS_HIGH 0x40000000
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH 0x3ff80000
|
||||
|
||||
/*DRAM1 is connected with Cache DBUS1*/
|
||||
#define DRAM1_ADDRESS_LOW 0x3f800000
|
||||
#define DRAM1_ADDRESS_HIGH 0x3fc00000
|
||||
#define SOC_DRAM1_ADDRESS_LOW 0x3f800000
|
||||
#define SOC_DRAM1_ADDRESS_HIGH 0x3fc00000
|
||||
|
||||
/*DPORT is connected with Cache DBUS2*/
|
||||
#define DPORT_ADDRESS_LOW 0x3f400000
|
||||
#define DPORT_ADDRESS_HIGH 0x3f800000
|
||||
#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
|
||||
#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
|
||||
#define SOC_DPORT_ADDRESS_LOW 0x3f400000
|
||||
#define SOC_DPORT_ADDRESS_HIGH 0x3f800000
|
||||
#define SOC_DPORT_CACHE_ADDRESS_LOW 0x3f500000
|
||||
#define SOC_DPORT_CACHE_ADDRESS_HIGH 0x3f800000
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
|
||||
#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
|
||||
#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
|
||||
#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM1(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM1, vaddr)
|
||||
#define SOC_ADDRESS_IN_DROM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DROM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM1(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM1, vaddr)
|
||||
#define SOC_ADDRESS_IN_DPORT(vaddr) SOC_ADDRESS_IN_BUS(SOC_DPORT, vaddr)
|
||||
#define SOC_ADDRESS_IN_DPORT_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DPORT_CACHE, vaddr)
|
||||
|
||||
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
|
||||
#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
|
||||
#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
|
||||
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
|
||||
#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
|
||||
#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT_CACHE)
|
||||
#define BUS_IRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_IRAM0_CACHE)
|
||||
#define BUS_IRAM1_CACHE_SIZE SOC_BUS_SIZE(SOC_IRAM1)
|
||||
#define BUS_IROM0_CACHE_SIZE SOC_BUS_SIZE(SOC_IROM0)
|
||||
#define BUS_DROM0_CACHE_SIZE SOC_BUS_SIZE(SOC_DROM0)
|
||||
#define BUS_DRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_DRAM0_CACHE)
|
||||
#define BUS_DRAM1_CACHE_SIZE SOC_BUS_SIZE(SOC_DRAM1)
|
||||
#define BUS_DPORT_CACHE_SIZE SOC_BUS_SIZE(SOC_DPORT_CACHE)
|
||||
|
||||
#define PRO_CACHE_IBUS0 0
|
||||
#define PRO_CACHE_IBUS0_MMU_START 0
|
||||
@@ -93,30 +93,30 @@ extern "C" {
|
||||
#define MMU_BUS_START(i) ((i) * 0x100)
|
||||
#define MMU_BUS_SIZE 0x100
|
||||
|
||||
#define MMU_INVALID BIT(14)
|
||||
#define MMU_VALID 0
|
||||
#define MMU_ACCESS_FLASH BIT(15)
|
||||
#define MMU_ACCESS_SPIRAM BIT(16)
|
||||
#define SOC_MMU_INVALID BIT(14)
|
||||
#define SOC_MMU_VALID 0
|
||||
#define SOC_MMU_ACCESS_FLASH BIT(15)
|
||||
#define SOC_MMU_ACCESS_SPIRAM BIT(16)
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(14), so value bits are 0x3fff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0x3fff
|
||||
#define SOC_MMU_VALID_VAL_MASK 0x3fff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 16384 * 64KB, means MMU can support 1GB paddr at most
|
||||
*/
|
||||
#define MMU_MAX_PADDR_PAGE_NUM 16384
|
||||
#define SOC_MMU_MAX_PADDR_PAGE_NUM 16384
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
* 0x4200_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK 0x3FFFFF
|
||||
#define SOC_MMU_VADDR_MASK 0x3FFFFF
|
||||
//MMU entry num
|
||||
#define MMU_ENTRY_NUM 384
|
||||
#define SOC_MMU_ENTRY_NUM 384
|
||||
|
||||
#define BUS_NUM_MASK 0x3
|
||||
|
||||
@@ -149,23 +149,23 @@ extern "C" {
|
||||
*/
|
||||
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF
|
||||
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
|
||||
#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (IRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (IRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (SOC_IRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (SOC_IRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
|
||||
#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (DROM0_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (DROM0_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (SOC_DROM0_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (SOC_DROM0_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
|
||||
#define SOC_MMU_DPORT_LINEAR_ADDRESS_LOW (DPORT_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH (DPORT_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DPORT_LINEAR_ADDRESS_LOW (SOC_DPORT_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH (SOC_DPORT_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
|
||||
#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (DRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (DRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (SOC_DRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (SOC_DRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -20,8 +20,8 @@ extern "C" {
|
||||
#define SOC_MMU_IROM0_PAGES_END (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_ADDR_MASK SOC_MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | SOC_MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
|
||||
#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -12,94 +12,50 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/*IRAM0 is connected with Cache IBUS0*/
|
||||
#define IRAM0_ADDRESS_LOW 0x40370000
|
||||
#define IRAM0_ADDRESS_HIGH 0x403E0000
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
|
||||
#define SOC_IRAM0_ADDRESS_LOW 0x40370000
|
||||
#define SOC_IRAM0_ADDRESS_HIGH 0x403E0000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x44000000
|
||||
|
||||
/*DRAM0 is connected with Cache DBUS0*/
|
||||
#define DRAM0_ADDRESS_LOW 0x3FC88000
|
||||
#define DRAM0_ADDRESS_HIGH 0x3FD00000
|
||||
#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH 0x3E000000
|
||||
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
|
||||
#define SOC_DRAM0_ADDRESS_LOW 0x3FC88000
|
||||
#define SOC_DRAM0_ADDRESS_HIGH 0x3FD00000
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW 0x3C000000
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH 0x3E000000
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
|
||||
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
|
||||
|
||||
#define CACHE_IBUS 0
|
||||
#define CACHE_IBUS_MMU_START 0
|
||||
#define CACHE_IBUS_MMU_END 0x800
|
||||
|
||||
#define CACHE_DBUS 1
|
||||
#define CACHE_DBUS_MMU_START 0
|
||||
#define CACHE_DBUS_MMU_END 0x800
|
||||
|
||||
//TODO, remove these cache function dependencies
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x800
|
||||
#define DCACHE_MMU_SIZE 0x800
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x800
|
||||
|
||||
#define MMU_INVALID BIT(14)
|
||||
#define MMU_VALID 0
|
||||
#define MMU_TYPE BIT(15)
|
||||
#define MMU_ACCESS_FLASH 0
|
||||
#define MMU_ACCESS_SPIRAM BIT(15)
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM 0x400000
|
||||
#define CACHE_MAX_LOCK_NUM 0x8000
|
||||
#define SOC_MMU_INVALID BIT(14)
|
||||
#define SOC_MMU_VALID 0
|
||||
#define SOC_MMU_TYPE BIT(15)
|
||||
#define SOC_MMU_ACCESS_FLASH 0
|
||||
#define SOC_MMU_ACCESS_SPIRAM BIT(15)
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(14), so value bits are 0x3fff
|
||||
*/
|
||||
#define MMU_VALID_VAL_MASK 0x3fff
|
||||
#define SOC_MMU_VALID_VAL_MASK 0x3fff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 16384 * 64KB, means MMU can support 1GB paddr at most
|
||||
*/
|
||||
#define MMU_MAX_PADDR_PAGE_NUM 16384
|
||||
#define SOC_MMU_MAX_PADDR_PAGE_NUM 16384
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & MMU_VADDR_MASK
|
||||
* 0x4200_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define MMU_VADDR_MASK 0x1FFFFFF
|
||||
#define SOC_MMU_VADDR_MASK 0x1FFFFFF
|
||||
//MMU entry num
|
||||
#define MMU_ENTRY_NUM 512
|
||||
|
||||
#define CACHE_ICACHE_LOW_SHIFT 0
|
||||
#define CACHE_ICACHE_HIGH_SHIFT 2
|
||||
#define CACHE_DCACHE_LOW_SHIFT 4
|
||||
#define CACHE_DCACHE_HIGH_SHIFT 6
|
||||
|
||||
#define CACHE_MEMORY_IBANK0_ADDR 0x40370000
|
||||
#define CACHE_MEMORY_IBANK1_ADDR 0x40374000
|
||||
|
||||
#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000
|
||||
#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000
|
||||
|
||||
#define SOC_MMU_ENTRY_NUM 512
|
||||
|
||||
#define SOC_MMU_DBUS_VADDR_BASE 0x3C000000
|
||||
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
|
||||
@@ -120,16 +76,16 @@ extern "C" {
|
||||
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
|
||||
* Under this condition, we use the max linear space.
|
||||
*/
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
@@ -141,6 +97,37 @@ extern "C" {
|
||||
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* ROM flash mmap driver needs below definitions
|
||||
*/
|
||||
#define BUS_IRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_DRAM0_CACHE)
|
||||
|
||||
#define CACHE_IBUS 0
|
||||
#define CACHE_IBUS_MMU_START 0
|
||||
#define CACHE_IBUS_MMU_END 0x800
|
||||
|
||||
#define CACHE_DBUS 1
|
||||
#define CACHE_DBUS_MMU_START 0
|
||||
#define CACHE_DBUS_MMU_END 0x800
|
||||
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x800
|
||||
#define DCACHE_MMU_SIZE 0x800
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x800
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -20,9 +20,9 @@ extern "C" {
|
||||
#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t))
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_ADDR_MASK SOC_MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | SOC_MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||
#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW
|
||||
|
||||
Reference in New Issue
Block a user