diff --git a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
index dc946200e12..02bf946fbed 100644
--- a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
+++ b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
@@ -38,15 +38,14 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
+#include "hal/assist_debug_ll.h"
 
 ESP_LOG_ATTR_TAG(TAG, "boot.esp32h4");
 
-// TODO: [ESP32H4] support core1 bus monitor IDF-12592
 static void wdt_reset_cpu0_info_enable(void)
 {
-    REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN);
-    REG_CLR_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_RST_EN);
-    REG_WRITE(BUS_MONITOR_CORE_0_RCD_EN_REG, BUS_MONITOR_CORE_0_RCD_PDEBUGEN | BUS_MONITOR_CORE_0_RCD_RECORDEN);
+    assist_debug_ll_enable_bus_clock(0, true);
+    assist_debug_ll_enable_pc_recording(0, true);
 }
 
 static void wdt_reset_info_dump(int cpu)
diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
index 70eb57c2af9..4aff280282d 100644
--- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@@ -54,8 +54,8 @@ ESP_LOG_ATTR_TAG(TAG, "boot.esp32p4");
 
 static void wdt_reset_cpu0_info_enable(void)
 {
-    _assist_debug_ll_enable_bus_clock(true);
-    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+    _assist_debug_ll_enable_bus_clock(0, true);
+    assist_debug_ll_enable_pc_recording(0, true);
 }
 
 static void wdt_reset_info_dump(int cpu)
diff --git a/components/esp_system/hw_stack_guard.c b/components/esp_system/hw_stack_guard.c
index 61774288c82..a6fb9dcfa6f 100644
--- a/components/esp_system/hw_stack_guard.c
+++ b/components/esp_system/hw_stack_guard.c
@@ -8,6 +8,7 @@
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/startup_internal.h"
 #include "soc/soc_caps.h"
+#include "soc/system_intr.h"
 #include "esp_rom_sys.h"
 #include "esp_cpu.h"
 
@@ -21,10 +22,12 @@ ESP_SYSTEM_INIT_FN(esp_hw_stack_guard_init, SECONDARY, ESP_SYSTEM_INIT_ALL_CORES
     PERIPH_RCC_ATOMIC()
 #endif
     {
-        assist_debug_ll_enable_bus_clock(true);
+        assist_debug_ll_enable_bus_clock(core_id, true);
         assist_debug_ll_reset_register(core_id);
     }
 
+    assist_debug_ll_enable_pc_recording(core_id, true);
+
     /* set interrupt to matrix */
     esp_rom_route_intr_matrix(core_id, ETS_ASSIST_DEBUG_INTR_SOURCE, ETS_ASSIST_DEBUG_INUM);
     esprv_int_set_type(ETS_ASSIST_DEBUG_INUM, INTR_TYPE_LEVEL);
diff --git a/components/hal/esp32c2/include/hal/assist_debug_ll.h b/components/hal/esp32c2/include/hal/assist_debug_ll.h
index 1fc98f882df..9f968b73e51 100644
--- a/components/hal/esp32c2/include/hal/assist_debug_ll.h
+++ b/components/hal/esp32c2/include/hal/assist_debug_ll.h
@@ -114,7 +114,11 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused
     return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
 }
 
-FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable)
 {
     SYSTEM.cpu_peri_clk_en.clk_en_assist_debug = enable;
 }
diff --git a/components/hal/esp32c3/include/hal/assist_debug_ll.h b/components/hal/esp32c3/include/hal/assist_debug_ll.h
index b0fabe37df8..7a228205ca9 100644
--- a/components/hal/esp32c3/include/hal/assist_debug_ll.h
+++ b/components/hal/esp32c3/include/hal/assist_debug_ll.h
@@ -114,7 +114,11 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused
     return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
 }
 
-FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable)
 {
     SYSTEM.cpu_peri_clk_en.reg_clk_en_assist_debug = enable;
 }
diff --git a/components/hal/esp32c5/include/hal/assist_debug_ll.h b/components/hal/esp32c5/include/hal/assist_debug_ll.h
index aaca9d9ae28..1745e1e7409 100644
--- a/components/hal/esp32c5/include/hal/assist_debug_ll.h
+++ b/components/hal/esp32c5/include/hal/assist_debug_ll.h
@@ -116,7 +116,11 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused
     return REG_READ(BUS_MONITOR_CORE_0_SP_PC_REG);
 }
 
-FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable)
 {
     PCR.assist_conf.assist_clk_en = enable;
 }
diff --git a/components/hal/esp32c6/include/hal/assist_debug_ll.h b/components/hal/esp32c6/include/hal/assist_debug_ll.h
index 8e19c09377f..46238f41d82 100644
--- a/components/hal/esp32c6/include/hal/assist_debug_ll.h
+++ b/components/hal/esp32c6/include/hal/assist_debug_ll.h
@@ -114,7 +114,11 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused
     return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
 }
 
-FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable)
 {
     PCR.assist_conf.assist_clk_en = enable;
 }
diff --git a/components/hal/esp32c61/include/hal/assist_debug_ll.h b/components/hal/esp32c61/include/hal/assist_debug_ll.h
index fd476e6dc4d..213b339a62b 100644
--- a/components/hal/esp32c61/include/hal/assist_debug_ll.h
+++ b/components/hal/esp32c61/include/hal/assist_debug_ll.h
@@ -116,7 +116,11 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused
     return REG_READ(BUS_MONITOR_CORE_0_SP_PC_REG);
 }
 
-FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable)
 {
     PCR.assist_conf.assist_clk_en = enable;
 }
diff --git a/components/hal/esp32h2/include/hal/assist_debug_ll.h b/components/hal/esp32h2/include/hal/assist_debug_ll.h
index 8e19c09377f..46238f41d82 100644
--- a/components/hal/esp32h2/include/hal/assist_debug_ll.h
+++ b/components/hal/esp32h2/include/hal/assist_debug_ll.h
@@ -114,7 +114,11 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(__attribute__((unused
     return REG_READ(ASSIST_DEBUG_CORE_0_SP_PC_REG);
 }
 
-FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable)
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable)
 {
     PCR.assist_conf.assist_clk_en = enable;
 }
diff --git a/components/hal/esp32h4/include/hal/assist_debug_ll.h b/components/hal/esp32h4/include/hal/assist_debug_ll.h
new file mode 100644
index 00000000000..159e8dc8f28
--- /dev/null
+++ b/components/hal/esp32h4/include/hal/assist_debug_ll.h
@@ -0,0 +1,179 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for DEBUG_ASSIST peripheral
+
+#pragma once
+
+#include "soc/assist_debug_reg.h"
+
+#ifndef __ASSEMBLER__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "esp_attr.h"
+#include "soc/pcr_struct.h"
+#include "soc/bus_monitor_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * The bus monitor peripheral provides stack overflow/underflow monitoring.
+ *
+ */
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_enable(uint32_t core_id)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_montr_ena.monitor_core_1_sp_spill_min_ena = 1;
+        BUS_MONITOR.monitor_core_1_montr_ena.monitor_core_1_sp_spill_max_ena = 1;
+    } else {
+        BUS_MONITOR.monitor_core_0_montr_ena.monitor_core_0_sp_spill_min_ena = 1;
+        BUS_MONITOR.monitor_core_0_montr_ena.monitor_core_0_sp_spill_max_ena = 1;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_monitor_disable(uint32_t core_id)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_montr_ena.monitor_core_1_sp_spill_min_ena = 0;
+        BUS_MONITOR.monitor_core_1_montr_ena.monitor_core_1_sp_spill_max_ena = 0;
+    } else {
+        BUS_MONITOR.monitor_core_0_montr_ena.monitor_core_0_sp_spill_min_ena = 0;
+        BUS_MONITOR.monitor_core_0_montr_ena.monitor_core_0_sp_spill_max_ena = 0;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_enable(uint32_t core_id)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_intr_ena.monitor_core_1_sp_spill_min_intr_ena = 1;
+        BUS_MONITOR.monitor_core_1_intr_ena.monitor_core_1_sp_spill_max_intr_ena = 1;
+    } else {
+        BUS_MONITOR.monitor_core_0_intr_ena.monitor_core_0_sp_spill_min_intr_ena = 1;
+        BUS_MONITOR.monitor_core_0_intr_ena.monitor_core_0_sp_spill_max_intr_ena = 1;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_disable(uint32_t core_id)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_intr_ena.monitor_core_1_sp_spill_min_intr_ena = 0;
+        BUS_MONITOR.monitor_core_1_intr_ena.monitor_core_1_sp_spill_max_intr_ena = 0;
+    } else {
+        BUS_MONITOR.monitor_core_0_intr_ena.monitor_core_0_sp_spill_min_intr_ena = 0;
+        BUS_MONITOR.monitor_core_0_intr_ena.monitor_core_0_sp_spill_max_intr_ena = 0;
+    }
+}
+
+FORCE_INLINE_ATTR bool assist_debug_ll_sp_spill_is_fired(uint32_t core_id)
+{
+    if (core_id) {
+        return BUS_MONITOR.monitor_core_1_intr_raw.monitor_core_1_sp_spill_min_raw || BUS_MONITOR.monitor_core_1_intr_raw.monitor_core_1_sp_spill_max_raw;
+    } else {
+        return BUS_MONITOR.monitor_core_0_intr_raw.monitor_core_0_sp_spill_min_raw || BUS_MONITOR.monitor_core_0_intr_raw.monitor_core_0_sp_spill_max_raw;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_interrupt_clear(uint32_t core_id)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_intr_clr.monitor_core_1_sp_spill_min_clr = 1;
+        BUS_MONITOR.monitor_core_1_intr_clr.monitor_core_1_sp_spill_max_clr = 1;
+    } else {
+        BUS_MONITOR.monitor_core_0_intr_clr.monitor_core_0_sp_spill_min_clr = 1;
+        BUS_MONITOR.monitor_core_0_intr_clr.monitor_core_0_sp_spill_max_clr = 1;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_min(uint32_t core_id, uint32_t min)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_sp_min.monitor_core_1_sp_min = min;
+    } else {
+        BUS_MONITOR.monitor_core_0_sp_min.monitor_core_0_sp_min = min;
+    }
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_min(uint32_t core_id)
+{
+    if (core_id) {
+        return BUS_MONITOR.monitor_core_1_sp_min.monitor_core_1_sp_min;
+    } else {
+        return BUS_MONITOR.monitor_core_0_sp_min.monitor_core_0_sp_min;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_sp_spill_set_max(uint32_t core_id, uint32_t max)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_sp_max.monitor_core_1_sp_max = max;
+    } else {
+        BUS_MONITOR.monitor_core_0_sp_max.monitor_core_0_sp_max = max;
+    }
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_max(uint32_t core_id)
+{
+    if (core_id) {
+        return BUS_MONITOR.monitor_core_1_sp_max.monitor_core_1_sp_max;
+    } else {
+        return BUS_MONITOR.monitor_core_0_sp_max.monitor_core_0_sp_max;
+    }
+}
+
+FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id)
+{
+    if (core_id) {
+        return BUS_MONITOR.monitor_core_1_sp_pc.monitor_core_1_sp_pc;
+    } else {
+        return BUS_MONITOR.monitor_core_0_sp_pc.monitor_core_0_sp_pc;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+    if (core_id) {
+        BUS_MONITOR.monitor_core_1_rcd_en.monitor_core_1_rcd_pdebugen = enable;
+        BUS_MONITOR.monitor_core_1_rcd_en.monitor_core_1_rcd_recorden = enable;
+    } else {
+        BUS_MONITOR.monitor_core_0_rcd_en.monitor_core_0_rcd_pdebugen = enable;
+        BUS_MONITOR.monitor_core_0_rcd_en.monitor_core_0_rcd_recorden = enable;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(uint32_t core_id, bool enable)
+{
+    if (core_id) {
+        PCR.assist_conf.assist1_clk_en = enable;
+    } else {
+        PCR.assist_conf.assist_clk_en = enable;
+    }
+}
+
+FORCE_INLINE_ATTR void assist_debug_ll_reset_register(uint32_t core_id)
+{
+    if (core_id) {
+        PCR.assist_conf.assist1_rst_en = true;
+        PCR.assist_conf.assist1_rst_en = false;
+    } else {
+        PCR.assist_conf.assist_rst_en = true;
+        PCR.assist_conf.assist_rst_en = false;
+    }
+}
+
+FORCE_INLINE_ATTR bool assist_debug_ll_is_debugger_active(void)
+{
+    return BUS_MONITOR.monitor_core_0_debug_mode.monitor_core_0_debug_module_active;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ASSEMBLER__
diff --git a/components/hal/esp32p4/include/hal/assist_debug_ll.h b/components/hal/esp32p4/include/hal/assist_debug_ll.h
index 677d25ba317..bd201c6d72d 100644
--- a/components/hal/esp32p4/include/hal/assist_debug_ll.h
+++ b/components/hal/esp32p4/include/hal/assist_debug_ll.h
@@ -116,7 +116,19 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id)
     return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_PC_REG : ASSIST_DEBUG_CORE_0_SP_PC_REG);
 }
 
-FORCE_INLINE_ATTR void _assist_debug_ll_enable_bus_clock(bool enable)
+FORCE_INLINE_ATTR void assist_debug_ll_enable_pc_recording(uint32_t core_id, bool enable)
+{
+    uint32_t reg = core_id ? ASSIST_DEBUG_CORE_1_RCD_EN_REG : ASSIST_DEBUG_CORE_0_RCD_EN_REG;
+    uint32_t bits = ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN;
+
+    if (enable) {
+        REG_SET_BIT(reg, bits);
+    } else {
+        REG_CLR_BIT(reg, bits);
+    }
+}
+
+FORCE_INLINE_ATTR void _assist_debug_ll_enable_bus_clock(__attribute__((unused)) uint32_t core_id, bool enable)
 {
     HP_SYS_CLKRST.soc_clk_ctrl0.reg_busmon_cpu_clk_en = enable;
     REG_SET_FIELD(ASSIST_DEBUG_CLOCK_GATE_REG, ASSIST_DEBUG_CLK_EN, enable);
@@ -124,15 +136,15 @@ FORCE_INLINE_ATTR void _assist_debug_ll_enable_bus_clock(bool enable)
 #define assist_debug_ll_enable_bus_clock(...) \
     (void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_enable_bus_clock(__VA_ARGS__)
 
-FORCE_INLINE_ATTR void _assist_debug_ll_reset_register(uint32_t core_id)
+FORCE_INLINE_ATTR void _assist_debug_ll_reset_register(__attribute__((unused)) uint32_t core_id)
 {
     /* esp32p4 has no assist_debug reset register: disable & clear interrupts manually.  */
-    assist_debug_ll_sp_spill_monitor_disable(core_id);
-    assist_debug_ll_sp_spill_interrupt_clear(core_id);
-    assist_debug_ll_sp_spill_set_min(core_id, 0);
-    assist_debug_ll_sp_spill_set_max(core_id, 0xffffffff);
-    /* Enable PC register storing when trigger stack monitor.  */
-    REG_WRITE(core_id ? ASSIST_DEBUG_CORE_1_RCD_EN_REG : ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_1_RCD_RECORDEN);
+    for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
+        assist_debug_ll_sp_spill_monitor_disable(i);
+        assist_debug_ll_sp_spill_interrupt_clear(i);
+        assist_debug_ll_sp_spill_set_min(i, 0);
+        assist_debug_ll_sp_spill_set_max(i, 0xffffffff);
+    }
 }
 #define assist_debug_ll_reset_register(...) \
     (void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_reset_register(__VA_ARGS__)
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
index 94a82349488..691551f4fde 100644
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -151,6 +151,10 @@ config SOC_CLK_TREE_SUPPORTED
     bool
     default y
 
+config SOC_ASSIST_DEBUG_SUPPORTED
+    bool
+    default y
+
 config SOC_WDT_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32h4/include/soc/assist_debug_reg.h b/components/soc/esp32h4/include/soc/assist_debug_reg.h
index bcba17de19e..96c15dd0e37 100644
--- a/components/soc/esp32h4/include/soc/assist_debug_reg.h
+++ b/components/soc/esp32h4/include/soc/assist_debug_reg.h
@@ -13,6 +13,10 @@
 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG          BUS_MONITOR_CORE_0_DEBUG_MODE_REG
 #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE     BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE
 
+#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG           BUS_MONITOR_CORE_0_MONTR_ENA_REG
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA        BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA        BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA
+
 #define ASSIST_DEBUG_CORE_0_SP_MIN_REG              BUS_MONITOR_CORE_0_SP_MIN_REG
 #define ASSIST_DEBUG_CORE_0_SP_MAX_REG              BUS_MONITOR_CORE_0_SP_MAX_REG
 
@@ -20,12 +24,24 @@
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN            BUS_MONITOR_CORE_0_RCD_PDEBUGEN
 #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN            BUS_MONITOR_CORE_0_RCD_RECORDEN
 
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG            BUS_MONITOR_CORE_0_INTR_ENA_REG
+
 #define ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG          BUS_MONITOR_CORE_1_DEBUG_MODE_REG
 #define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE     BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE
 
+#define ASSIST_DEBUG_CORE_1_MONTR_ENA_REG           BUS_MONITOR_CORE_1_MONTR_ENA_REG
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA        BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA        BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA
+
 #define ASSIST_DEBUG_CORE_1_SP_MIN_REG              BUS_MONITOR_CORE_1_SP_MIN_REG
 #define ASSIST_DEBUG_CORE_1_SP_MAX_REG              BUS_MONITOR_CORE_1_SP_MAX_REG
 
 #define ASSIST_DEBUG_CORE_1_RCD_EN_REG              BUS_MONITOR_CORE_1_RCD_EN_REG
 #define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN            BUS_MONITOR_CORE_1_RCD_PDEBUGEN
 #define ASSIST_DEBUG_CORE_1_RCD_RECORDEN            BUS_MONITOR_CORE_1_RCD_RECORDEN
+
+#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG            BUS_MONITOR_CORE_1_INTR_ENA_REG
+
+#define ASSIST_DEBUG_SP_SPILL_BITS                  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA | ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA)
+#define ASSIST_DEBUG_CORE_0_MONITOR_REG             ASSIST_DEBUG_CORE_0_MONTR_ENA_REG
+#define ASSIST_DEBUG_CORE_1_MONITOR_REG             ASSIST_DEBUG_CORE_1_MONTR_ENA_REG
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index 5599f395bac..d2f20f2a26c 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -83,7 +83,7 @@
 // #define SOC_LP_PERIPHERALS_SUPPORTED    1
 #define SOC_REG_I2C_SUPPORTED           1
 #define SOC_CLK_TREE_SUPPORTED          1
-// #define SOC_ASSIST_DEBUG_SUPPORTED      1    // TODO: [ESP32H4] IDF-12310
+#define SOC_ASSIST_DEBUG_SUPPORTED      1
 #define SOC_WDT_SUPPORTED               1
 #define SOC_SPI_FLASH_SUPPORTED         1
 #define SOC_SPIRAM_SUPPORTED            1
diff --git a/components/soc/esp32h4/include/soc/system_intr.h b/components/soc/esp32h4/include/soc/system_intr.h
index 0677a14f4ad..bab0bbf4727 100644
--- a/components/soc/esp32h4/include/soc/system_intr.h
+++ b/components/soc/esp32h4/include/soc/system_intr.h
@@ -15,3 +15,5 @@
 
 #define SYS_TG0_WDT_INTR_SOURCE         ETS_TG0_WDT_INTR_SOURCE
 #define SYS_TG1_WDT_INTR_SOURCE         ETS_TG1_WDT_INTR_SOURCE
+
+#define ETS_ASSIST_DEBUG_INTR_SOURCE    ETS_BUS_MONITOR_INTR_SOURCE
diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld
index a21af72147f..3c3f88eb1e3 100644
--- a/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld
+++ b/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld
@@ -6,7 +6,7 @@
 
 PROVIDE ( TRACE0              = 0x60000000 );
 PROVIDE ( TRACE1              = 0x60001000 );
-PROVIDE ( ASSIST_DEBUG        = 0x60002000 );
+PROVIDE ( BUS_MONITOR         = 0x60002000 );
 PROVIDE ( INTPRI              = 0x60005000 );
 PROVIDE ( CACHE               = 0x60008000 );
 PROVIDE ( GPSPI2              = 0x60010000 );
diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld
index e433aa48f5d..b74a2c3f7f3 100644
--- a/components/soc/esp32h4/ld/esp32h4.peripherals.ld
+++ b/components/soc/esp32h4/ld/esp32h4.peripherals.ld
@@ -6,7 +6,7 @@
 
 PROVIDE ( TRACE0              = 0x60000000 );
 PROVIDE ( TRACE1              = 0x60001000 );
-PROVIDE ( ASSIST_DEBUG        = 0x60002000 );
+PROVIDE ( BUS_MONITOR         = 0x60002000 );
 PROVIDE ( INTPRI              = 0x60005000 );
 PROVIDE ( CACHE               = 0x60008000 );
 PROVIDE ( GPSPI2              = 0x60010000 );
diff --git a/components/soc/esp32h4/register/soc/bus_monitor_reg.h b/components/soc/esp32h4/register/soc/bus_monitor_reg.h
index 554a1f6b3fb..44cd7ded38e 100644
--- a/components/soc/esp32h4/register/soc/bus_monitor_reg.h
+++ b/components/soc/esp32h4/register/soc/bus_monitor_reg.h
@@ -5,7 +5,6 @@
  */
 #pragma once
 
-#include <stdint.h>
 #include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
diff --git a/tools/test_apps/system/build_tests/no_hwsg/README.md b/tools/test_apps/system/build_tests/no_hwsg/README.md
index 971ab1a5e4c..b7f481ca782 100644
--- a/tools/test_apps/system/build_tests/no_hwsg/README.md
+++ b/tools/test_apps/system/build_tests/no_hwsg/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
 
 This project tests building with the no_hwsg configuration.