change(esp_system): add iram opt for rtc clk resart cases

components/esp_hw_support/port/esp32h4/rtc_clk.c

@@ -168,7 +168,7 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
  * Must satisfy: cpu_freq = XTAL_FREQ / div.
  * Does not disable the PLL.
  */
-static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
+FORCE_IRAM_ATTR static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
 {
     // let f_cpu = f_ahb
     clk_ll_ahb_set_divider(1);

components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c

@@ -480,3 +480,33 @@ TEST_CASE("Output 8M clock to GPIO25", "[ignore]")
     pull_out_clk(RTC_IO_DEBUG_SEL0_8M);
 }
 #endif
+
+#if !CONFIG_RTC_CLK_FUNC_IN_IRAM
+static void do_restart(void)
+{
+    esp_restart();
+}
+
+#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
+static void do_restart_from_app_cpu(void)
+{
+    xTaskCreatePinnedToCore((TaskFunction_t) &do_restart, "restart", 2048, NULL, 5, NULL, 1);
+    vTaskDelay(2);
+}
+#endif
+
+static void check_reset_reason_sw(void)
+{
+    TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
+}
+
+TEST_CASE_MULTIPLE_STAGES("test rtc_clk in flash after restart", "[rtc_clk]",
+                          do_restart,
+                          check_reset_reason_sw);
+
+#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
+TEST_CASE_MULTIPLE_STAGES("test rtc_clk in flash after restart from APP CPU", "[rtc_clk]",
+                          do_restart_from_app_cpu,
+                          check_reset_reason_sw);
+#endif
+#endif

components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
 
 import pytest
@@ -33,3 +33,21 @@ def test_rtc_no_xtal32k(dut: IdfDut) -> None:
 @idf_parametrize('target', soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1'), indirect=['target'])
 def test_rtc_calib_compensation_across_dslp(case_tester: CaseTester) -> None:
     case_tester.run_all_multi_stage_cases()
+
+
+@pytest.mark.flash_suspend
+@pytest.mark.temp_skip_ci(targets=['esp32h2'], reason='flash clock lose in startup')  # TODO [ESP32H2]: IDF-15212
+@pytest.mark.parametrize(
+    'config',
+    [
+        'rtc_clk_flash',
+    ],
+    indirect=True,
+)
+@idf_parametrize(
+    'target',
+    soc_filtered_targets('SOC_CLK_TREE_SUPPORTED == 1 and IDF_TARGET not in ["esp32", "esp32s2"]'),
+    indirect=['target'],
+)
+def test_rtc_clk_flash(case_tester: CaseTester) -> None:
+    case_tester.run_all_multi_stage_cases()

components/esp_hw_support/test_apps/rtc_clk/sdkconfig.ci.rtc_clk_flash

@@ -0,0 +1,4 @@
+CONFIG_RTC_CLK_FUNC_IN_IRAM=n
+CONFIG_SPI_FLASH_AUTO_SUSPEND=y
+# Now the runners are massively using xmc-c chips, to be removed when xmc-d goes massive production.
+CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND=y

components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.default

@@ -2,3 +2,6 @@
 # Used for testing stack smashing protection
 CONFIG_COMPILER_STACK_CHECK=y
 CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
+CONFIG_ESP_PERIPH_CTRL_FUNC_IN_IRAM=n
+CONFIG_RTC_CLK_FUNC_IN_IRAM=n
+CONFIG_RTC_TIME_FUNC_IN_IRAM=n