feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets

Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3, ESP32-P4 and
ESP32-H4 to expose the number of FSLS USB_WRAP PHYs available on each
target. This separates FSLS USB_WRAP support from OTG/UTMI support so
that downstream code can gate FSLS PHY handling independently.

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -747,6 +747,10 @@ config SOC_USB_OTG_PERIPH_NUM
     int
     default 1
 
+config SOC_USB_FSLS_PHY_NUM
+    int
+    default 1
+
 config SOC_SHA_DMA_MAX_BUFFER_SIZE
     int
     default 3968

components/soc/esp32s2/include/soc/soc_caps.h

@@ -341,6 +341,7 @@
 
 /*-------------------------- USB CAPS ----------------------------------------*/
 #define SOC_USB_OTG_PERIPH_NUM          (1U)
+#define SOC_USB_FSLS_PHY_NUM            (1U)
 
 /*--------------------------- SHA CAPS ---------------------------------------*/
 /* Max amount of bytes in a single DMA operation is 4095,