feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets

Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3, ESP32-P4 and
ESP32-H4 to expose the number of FSLS USB_WRAP PHYs available on each
target. This separates FSLS USB_WRAP support from OTG/UTMI support so
that downstream code can gate FSLS PHY handling independently.

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1163,6 +1163,10 @@ config SOC_USB_OTG_PERIPH_NUM
     int
     default 2
 
+config SOC_USB_FSLS_PHY_NUM
+    int
+    default 1
+
 config SOC_USB_UTMI_PHY_NUM
     int
     default 1

components/soc/esp32p4/include/soc/soc_caps.h

@@ -430,6 +430,7 @@
 
 // USB OTG Caps
 #define SOC_USB_OTG_PERIPH_NUM          (2U)
+#define SOC_USB_FSLS_PHY_NUM            (1U)
 
 // USB PHY Caps
 #define SOC_USB_UTMI_PHY_NUM            (1U)