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i2s: bringup i2s on esp32c6

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This commit is contained in:
laokaiyao
2022-09-15 20:03:39 +08:00
parent 7197e987cb
commit bae4944b90
16 changed files with 1208 additions and 29 deletions
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components/soc/esp32c6/CMakeLists.txt
-1
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@@ -20,7 +20,6 @@ list(REMOVE_ITEM srcs
"adc_periph.c" # TODO: IDF-5310
"dedic_gpio_periph.c" # TODO: IDF-5331
"ledc_periph.c" # TODO: IDF-5328
"i2s_periph.c" # TODO: IDF-5314
"i2c_periph.c" # TODO: IDF-5326
"temperature_sensor_periph.c" # TODO: IDF-5322
)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+4
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@@ -43,6 +43,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
components/soc/esp32c6/include/soc/clk_tree_defs.h
+10 -1
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@@ -215,14 +215,23 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M}
#if CONFIG_IDF_ENV_FPGA
#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL}
#else
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
#endif
/**
* @brief I2S clock source enum
*/
typedef enum {
#if CONFIG_IDF_ENV_FPGA
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
#else
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
#endif
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
components/soc/esp32c6/include/soc/i2s_struct.h
+8 -8
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@@ -255,7 +255,7 @@ typedef union {
*/
uint32_t rx_clk_active:1;
/** rx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
* Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/
uint32_t rx_clk_sel:2;
/** mclk_sel : R/W; bitpos: [29]; default: 0;
@@ -448,7 +448,7 @@ typedef union {
uint32_t val;
} i2s_rx_tdm_ctrl_reg_t;
/** Type of rxeof_num register
/** Type of rx_eof_num register
* I2S RX data number control register.
*/
typedef union {
@@ -461,7 +461,7 @@ typedef union {
uint32_t reserved_12:20;
};
uint32_t val;
} i2s_rxeof_num_reg_t;
} i2s_rx_eof_num_reg_t;
/** Group: TX Control and configuration registers */
@@ -627,7 +627,7 @@ typedef union {
*/
uint32_t tx_clk_active:1;
/** tx_clk_sel : R/W; bitpos: [28:27]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
* Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in.
*/
uint32_t tx_clk_sel:2;
@@ -914,7 +914,7 @@ typedef union {
uint32_t val;
} i2s_lc_hung_conf_reg_t;
/** Type of conf_sigle_data register
/** Type of conf_single_data register
* I2S signal data register
*/
typedef union {
@@ -925,7 +925,7 @@ typedef union {
uint32_t single_data:32;
};
uint32_t val;
} i2s_conf_sigle_data_reg_t;
} i2s_conf_single_data_reg_t;
/** Group: TX status registers */
@@ -1005,8 +1005,8 @@ typedef struct i2s_dev_t {
volatile i2s_rx_timing_reg_t rx_timing;
volatile i2s_tx_timing_reg_t tx_timing;
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
volatile i2s_rxeof_num_reg_t rxeof_num;
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
volatile i2s_rx_eof_num_reg_t rx_eof_num;
volatile i2s_conf_single_data_reg_t conf_single_data;
volatile i2s_state_reg_t state;
volatile i2s_etm_conf_reg_t etm_conf;
uint32_t reserved_074[3];
components/soc/esp32c6/include/soc/pcr_struct.h
+2 -2
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@@ -607,7 +607,7 @@ typedef union {
*/
uint32_t i2s_tx_clkm_div_num:8;
/** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
* Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
* I2S_MCLK_in.
*/
uint32_t i2s_tx_clkm_sel:2;
@@ -661,7 +661,7 @@ typedef union {
*/
uint32_t i2s_rx_clkm_div_num:8;
/** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
* Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
* Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
*/
uint32_t i2s_rx_clkm_sel:2;
/** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
components/soc/esp32c6/include/soc/soc_caps.h
+1 -2
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@@ -40,7 +40,7 @@
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-5314
#define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-5320
// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-5318
// #define SOC_LEDC_SUPPORTED 1 // TODO: IDF-5328
@@ -181,7 +181,6 @@
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
// TODO: IDF-5314 (Copy from esp32c3, need check)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_HW_VERSION_2 (1)